blob: 3af741c0b3a9134fc5c54d768a00fbd5702e5e97 [file] [log] [blame]
Felix Held80434a62023-12-13 23:11:45 +01001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <amdblocks/acpi.h>
4#include <amdblocks/acpimmio.h>
5#include <amdblocks/amd_pci_util.h>
6#include <amdblocks/gpio.h>
7#include <amdblocks/smi.h>
8#include <bootstate.h>
9#include <cpu/x86/smm.h>
Felix Held80434a62023-12-13 23:11:45 +010010#include <soc/amd_pci_int_defs.h>
11#include <soc/smi.h>
12#include <soc/southbridge.h>
13
14/*
15 * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
16 * provides a visible association with the index, therefore helping
17 * maintainability of table. If a new index/name is defined in
18 * amd_pci_int_defs.h, just add the pair at the end of this table.
19 * Order is not important.
20 */
21static const struct irq_idx_name irq_association[] = {
22 { PIRQ_A, "INTA#" },
23 { PIRQ_B, "INTB#" },
24 { PIRQ_C, "INTC#" },
25 { PIRQ_D, "INTD#" },
26 { PIRQ_E, "INTE#" },
27 { PIRQ_F, "INTF#/GENINT2" },
28 { PIRQ_G, "INTG#" },
29 { PIRQ_H, "INTH#" },
30 { PIRQ_MISC, "Misc" },
31 { PIRQ_MISC0, "Misc0" },
32 { PIRQ_HPET_L, "HPET_L" },
33 { PIRQ_HPET_H, "HPET_H" },
34 { PIRQ_SIRQA, "Ser IRQ INTA" },
35 { PIRQ_SIRQB, "Ser IRQ INTB" },
36 { PIRQ_SIRQC, "Ser IRQ INTC" },
37 { PIRQ_SIRQD, "Ser IRQ INTD" },
38 { PIRQ_SCI, "SCI" },
39 { PIRQ_SMBUS, "SMBUS" },
40 { PIRQ_ASF, "ASF" },
41 { PIRQ_PMON, "PerMon" },
42 { PIRQ_SDIO, "SDIO" },
43 { PIRQ_GPP0, "GPP0" },
44 { PIRQ_GPP1, "GPP1" },
45 { PIRQ_GPP2, "GPP2" },
46 { PIRQ_GPP3, "GPP3" },
47 { PIRQ_GSCI, "GEvent SCI" },
48 { PIRQ_GSMI, "GEvent SMI" },
49 { PIRQ_GPIO, "GPIO" },
50 { PIRQ_I2C0, "I2C0" },
51 { PIRQ_I2C1, "I2C1" },
52 { PIRQ_I2C2, "I2C2" },
53 { PIRQ_I2C3, "I2C3" },
54 { PIRQ_UART0, "UART0" },
55 { PIRQ_UART1, "UART1" },
56 { PIRQ_I2C4, "I2C4" },
57 { PIRQ_I2C5, "I2C5" },
58 { PIRQ_UART2, "UART2" },
59 { PIRQ_UART3, "UART3" },
60};
61
62const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
63{
64 *size = ARRAY_SIZE(irq_association);
65 return irq_association;
66}
67
68static void set_pci_irqs(void)
69{
70 /* Write PCI_INTR regs 0xC00/0xC01 */
71 write_pci_int_table();
72
73 /* TODO: PIRQ configuration */
74}
75
Felix Heldf0c67122023-12-14 18:52:40 +010076static void fch_init_acpi_ports(void)
77{
78 /* Configure and enable APMC SMI Command Port */
79 pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
80 configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
81}
82
Felix Helddc12a382024-01-16 00:50:46 +010083void fch_init(void *chip_info)
Felix Held80434a62023-12-13 23:11:45 +010084{
85 set_pci_irqs();
Felix Heldf0c67122023-12-14 18:52:40 +010086 fch_init_acpi_ports();
Felix Held80434a62023-12-13 23:11:45 +010087}