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Felix Held8a3d4d52021-01-13 03:06:21 +01001/* SPDX-License-Identifier: GPL-2.0-only */
2
Felix Helddea4e0f2021-09-22 20:05:53 +02003#include <amdblocks/gpio.h>
Felix Held8a3d4d52021-01-13 03:06:21 +01004#include <amdblocks/uart.h>
5#include <commonlib/helpers.h>
6#include <device/mmio.h>
Elyes Haouas5e2602a2023-01-14 05:46:25 +01007#include <gpio.h>
Felix Held117823e2021-06-15 16:33:29 +02008#include <soc/aoac_defs.h>
Felix Heldc6e4cc82022-10-18 19:22:21 +02009#include <soc/iomap.h>
Felix Held8a3d4d52021-01-13 03:06:21 +010010#include <soc/southbridge.h>
11#include <soc/uart.h>
12#include <types.h>
13
Felix Heldd2ebe162022-10-18 18:16:14 +020014static const struct soc_uart_ctrlr_info uart_info[] = {
Felix Heldd85f25f2022-10-18 18:23:28 +020015 [0] = { APU_UART0_BASE, FCH_AOAC_DEV_UART0, "FUR0", {
Felix Held8a3d4d52021-01-13 03:06:21 +010016 PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
17 PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
Felix Heldd85f25f2022-10-18 18:23:28 +020018 } },
19 [1] = { APU_UART1_BASE, FCH_AOAC_DEV_UART1, "FUR1", {
Felix Held8a3d4d52021-01-13 03:06:21 +010020 PAD_NF(GPIO_140, UART1_TXD, PULL_NONE),
21 PAD_NF(GPIO_142, UART1_RXD, PULL_NONE),
Felix Heldd85f25f2022-10-18 18:23:28 +020022 } },
Felix Held8a3d4d52021-01-13 03:06:21 +010023};
24
Felix Held97e61252022-10-18 19:03:20 +020025const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs)
Felix Held8a3d4d52021-01-13 03:06:21 +010026{
Felix Held9fde8892022-10-18 20:21:58 +020027 *num_ctrlrs = ARRAY_SIZE(uart_info);
28 return uart_info;
Felix Held8a3d4d52021-01-13 03:06:21 +010029}
30
31void clear_uart_legacy_config(void)
32{
Felix Held25866fe2022-09-29 16:06:45 +020033 write16p(FCH_LEGACY_UART_DECODE, 0);
Felix Held8a3d4d52021-01-13 03:06:21 +010034}