| Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 2 | |
| Michael Niewöhner | 90df916 | 2020-10-13 22:58:28 +0200 | [diff] [blame] | 3 | #include <types.h> |
| Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 4 | #include <cpu/x86/msr.h> |
| 5 | #include <cpu/intel/speedstep.h> |
| Elyes HAOUAS | 45ce5d8 | 2021-01-31 09:15:30 +0100 | [diff] [blame] | 6 | |
| Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 7 | #include "model_2065x.h" |
| 8 | |
| Alexander Couzens | f251a6d | 2015-01-28 01:51:04 +0100 | [diff] [blame] | 9 | /* MSR Documentation based on |
| 10 | * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)" |
| 11 | * Document Number 504790 |
| 12 | * Revision 1.6.0, June 2012 */ |
| 13 | |
| Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 14 | void intel_model_2065x_finalize_smm(void) |
| 15 | { |
| Alexander Couzens | f251a6d | 2015-01-28 01:51:04 +0100 | [diff] [blame] | 16 | /* Lock C-State MSR */ |
| Michael Niewöhner | 90df916 | 2020-10-13 22:58:28 +0200 | [diff] [blame] | 17 | msr_set(MSR_PKG_CST_CONFIG_CONTROL, BIT(15)); |
| Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 18 | |
| Elyes HAOUAS | ece2696 | 2018-08-07 12:24:16 +0200 | [diff] [blame] | 19 | /* Lock TM interrupts - route thermal events to all processors */ |
| Michael Niewöhner | 90df916 | 2020-10-13 22:58:28 +0200 | [diff] [blame] | 20 | msr_set(MSR_MISC_PWR_MGMT, BIT(22)); |
| Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 21 | } |