David Wu | 4cea00a | 2020-04-24 16:13:07 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
David Wu | 4cea00a | 2020-04-24 16:13:07 +0800 | [diff] [blame] | 2 | |
Nick Vaccaro | 2f78ce0 | 2021-02-16 19:06:16 -0800 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
David Wu | 4cea00a | 2020-04-24 16:13:07 +0800 | [diff] [blame] | 4 | #include <baseboard/gpio.h> |
| 5 | #include <baseboard/variants.h> |
| 6 | #include <commonlib/helpers.h> |
| 7 | |
| 8 | /* Pad configuration in ramstage */ |
David Wu | a85af8e | 2021-05-13 20:00:09 +0800 | [diff] [blame] | 9 | static const struct pad_config override_gpio_table[] = { |
| 10 | /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ |
| 11 | PAD_CFG_GPO(GPP_A7, 1, DEEP), |
| 12 | /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ |
| 13 | PAD_CFG_GPO(GPP_A8, 1, DEEP), |
| 14 | /* A10 : I2S2_RXD ==> EN_SPKR_PA */ |
| 15 | PAD_CFG_GPO(GPP_A10, 1, DEEP), |
| 16 | /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ |
| 17 | PAD_CFG_GPO(GPP_A13, 1, DEEP), |
| 18 | /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ |
| 19 | PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), |
| 20 | /* A18 : DDSP_HPDB ==> HDMI_HPD */ |
| 21 | PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), |
| 22 | /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ |
| 23 | PAD_CFG_GPO(GPP_A22, 1, DEEP), |
| 24 | /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ |
| 25 | PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), |
David Wu | 4cea00a | 2020-04-24 16:13:07 +0800 | [diff] [blame] | 26 | |
David Wu | a85af8e | 2021-05-13 20:00:09 +0800 | [diff] [blame] | 27 | /* B2 : VRALERT# ==> EN_PP3300_SSD */ |
| 28 | PAD_CFG_GPO(GPP_B2, 1, DEEP), |
| 29 | /* B3 : CPU_GP2 ==> PEN_DET_ODL */ |
| 30 | PAD_CFG_GPI_GPIO_DRIVER(GPP_B3, NONE, PLTRST), |
| 31 | /* B5 : ISH_I2C0_CVF_SDA */ |
| 32 | PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), |
| 33 | /* B6 : ISH_I2C0_CVF_SCL */ |
| 34 | PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), |
| 35 | /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ |
| 36 | PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), |
| 37 | /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ |
| 38 | PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), |
| 39 | /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ |
| 40 | PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), |
| 41 | /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ |
| 42 | PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), |
| 43 | /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ |
| 44 | PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), |
| 45 | /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ |
| 46 | PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), |
| 47 | /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ |
| 48 | PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), |
| 49 | /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ |
| 50 | PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), |
| 51 | /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ |
| 52 | PAD_NC(GPP_B23, DN_20K), |
| 53 | |
| 54 | /* C0 : SMBCLK ==> EN_PP3300_WLAN */ |
| 55 | PAD_CFG_GPO(GPP_C0, 1, DEEP), |
| 56 | /* C2 : SMBALERT# ==> GPP_C2_STRAP */ |
| 57 | PAD_NC(GPP_C2, DN_20K), |
| 58 | /* C3 : SML0CLK ==> USB4_SMB_SCL */ |
| 59 | PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), |
| 60 | /* C4 : SML0DATA ==> USB4_SMB_SDA */ |
| 61 | PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), |
| 62 | /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */ |
| 63 | PAD_NC(GPP_C5, DN_20K), |
| 64 | /* C7 : SML1DATA ==> EN_PP5000_PEN */ |
| 65 | PAD_CFG_GPO(GPP_C7, 1, DEEP), |
| 66 | /* C10 : UART0_RTS# ==> USI_RST_L */ |
| 67 | PAD_CFG_GPO(GPP_C10, 1, DEEP), |
| 68 | /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ |
| 69 | PAD_CFG_GPO(GPP_C13, 1, DEEP), |
| 70 | /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ |
| 71 | PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), |
| 72 | /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ |
| 73 | PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), |
| 74 | /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ |
| 75 | PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), |
| 76 | /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ |
| 77 | PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), |
| 78 | /* C20 : UART2_RXD ==> FPMCU_INT_L */ |
| 79 | PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), |
| 80 | /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ |
| 81 | PAD_CFG_GPO(GPP_C22, 0, DEEP), |
| 82 | |
| 83 | /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ |
| 84 | PAD_CFG_GPI(GPP_D0, NONE, DEEP), |
| 85 | /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ |
| 86 | PAD_CFG_GPI(GPP_D1, NONE, DEEP), |
| 87 | /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ |
| 88 | PAD_CFG_GPI(GPP_D2, NONE, DEEP), |
| 89 | /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ |
| 90 | PAD_CFG_GPI(GPP_D3, NONE, DEEP), |
| 91 | /* D4 : IMGCLKOUT0 ==> FCAM_RST_L */ |
| 92 | PAD_CFG_GPO(GPP_D4, 0, PLTRST), |
| 93 | /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ |
| 94 | PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), |
| 95 | /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ |
| 96 | PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), |
| 97 | /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ |
| 98 | PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), |
| 99 | /* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */ |
| 100 | PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7), |
| 101 | /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ |
| 102 | PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), |
| 103 | /* D11 : ISH_SPI_MISO ==> PCH_GSPI2_CVF_MISO */ |
| 104 | PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7), |
| 105 | /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ |
| 106 | PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), |
| 107 | /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ |
| 108 | PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), |
| 109 | /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ |
| 110 | PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), |
| 111 | /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ |
| 112 | PAD_CFG_GPO(GPP_D16, 1, DEEP), |
| 113 | /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ |
| 114 | PAD_CFG_GPO(GPP_D17, 1, DEEP), |
| 115 | |
| 116 | /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ |
| 117 | PAD_CFG_GPI_SCI(GPP_E1, NONE, DEEP, EDGE_SINGLE, NONE), |
| 118 | /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ |
| 119 | PAD_CFG_GPI(GPP_E2, NONE, DEEP), |
| 120 | /* E3 : CPU_GP0 ==> USI_REPORT_EN */ |
| 121 | PAD_CFG_GPO(GPP_E3, 1, DEEP), |
| 122 | /* E7 : CPU_GP1 ==> USI_INT */ |
| 123 | PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), |
| 124 | /* E8 : SPI1_CS1# ==> SLP_S0IX */ |
| 125 | PAD_CFG_GPO(GPP_E8, 0, DEEP), |
| 126 | /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ |
| 127 | PAD_CFG_GPI(GPP_E11, NONE, DEEP), |
| 128 | /* E12 : SPI1_MISO_IO1 ==> PEN_OC_ODL */ |
| 129 | PAD_CFG_GPI(GPP_E12, NONE, DEEP), |
| 130 | /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ |
| 131 | PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT), |
| 132 | /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ |
| 133 | PAD_CFG_GPI(GPP_E16, NONE, DEEP), |
| 134 | /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ |
| 135 | PAD_CFG_GPO(GPP_E17, 1, DEEP), |
| 136 | /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ |
| 137 | PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), |
| 138 | |
| 139 | /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ |
| 140 | PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), |
| 141 | /* F7 : GPPF7_STRAP */ |
| 142 | PAD_NC(GPP_F7, DN_20K), |
| 143 | /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ |
| 144 | PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), |
| 145 | /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ |
| 146 | PAD_CFG_GPO(GPP_F11, 1, DEEP), |
| 147 | /* F12 : GSXDOUT ==> WWAN_RST_ODL */ |
| 148 | PAD_CFG_GPI(GPP_F12, NONE, DEEP), |
| 149 | /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ |
| 150 | PAD_CFG_GPO(GPP_F13, 1, DEEP), |
| 151 | /* F14 : GSXDIN ==> SAR0_INT_L */ |
| 152 | PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), |
| 153 | /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ |
| 154 | PAD_CFG_GPO(GPP_F16, 1, DEEP), |
| 155 | /* F17 : WWAN_RF_DISABLE_ODL */ |
| 156 | PAD_CFG_GPO(GPP_F17, 1, DEEP), |
| 157 | /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ |
| 158 | PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), |
| 159 | /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ |
| 160 | PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), |
| 161 | |
| 162 | /* H0 : GPPH0_BOOT_STRAP1 */ |
| 163 | PAD_NC(GPP_H0, DN_20K), |
| 164 | /* H1 : GPPH1_BOOT_STRAP2 */ |
| 165 | PAD_NC(GPP_H1, DN_20K), |
| 166 | /* H2 : GPPH2_BOOT_STRAP3 */ |
| 167 | PAD_NC(GPP_H2, DN_20K), |
| 168 | /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ |
| 169 | PAD_CFG_GPO(GPP_H3, 1, DEEP), |
| 170 | /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SAR1_SDA */ |
| 171 | PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), |
| 172 | /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SAR1_SCL */ |
| 173 | PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), |
| 174 | /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ |
| 175 | PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), |
| 176 | /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ |
| 177 | PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), |
| 178 | /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ |
| 179 | PAD_CFG_GPI(GPP_H12, NONE, DEEP), |
| 180 | /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ |
| 181 | PAD_CFG_GPI(GPP_H13, NONE, DEEP), |
| 182 | /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ |
| 183 | PAD_CFG_GPI(GPP_H15, NONE, DEEP), |
| 184 | /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ |
| 185 | PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), |
| 186 | /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ |
| 187 | PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), |
| 188 | /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ |
| 189 | PAD_CFG_GPI(GPP_H19, NONE, DEEP), |
| 190 | /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ |
| 191 | PAD_CFG_GPO(GPP_H20, 0, DEEP), |
| 192 | /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ |
| 193 | PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), |
| 194 | /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ |
| 195 | PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), |
| 196 | |
| 197 | /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ |
| 198 | PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), |
| 199 | /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ |
| 200 | PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), |
| 201 | /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ |
| 202 | PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), |
| 203 | /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ |
| 204 | PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), |
| 205 | /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ |
| 206 | PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), |
| 207 | /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ |
| 208 | PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), |
| 209 | /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ |
| 210 | PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), |
| 211 | |
| 212 | /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ |
| 213 | PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), |
| 214 | /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ |
| 215 | PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), |
| 216 | /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ |
| 217 | PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), |
| 218 | /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ |
| 219 | PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), |
| 220 | /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ |
| 221 | PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), |
| 222 | /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ |
| 223 | PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), |
| 224 | |
| 225 | /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ |
| 226 | PAD_CFG_NF(GPD9, NONE, DEEP, NF1), |
David Wu | 4cea00a | 2020-04-24 16:13:07 +0800 | [diff] [blame] | 227 | }; |
| 228 | |
David Wu | a85af8e | 2021-05-13 20:00:09 +0800 | [diff] [blame] | 229 | const struct pad_config *variant_override_gpio_table(size_t *num) |
David Wu | 4cea00a | 2020-04-24 16:13:07 +0800 | [diff] [blame] | 230 | { |
David Wu | a85af8e | 2021-05-13 20:00:09 +0800 | [diff] [blame] | 231 | *num = ARRAY_SIZE(override_gpio_table); |
| 232 | return override_gpio_table; |
David Wu | 4cea00a | 2020-04-24 16:13:07 +0800 | [diff] [blame] | 233 | } |
| 234 | |
| 235 | /* Early pad configuration in bootblock */ |
| 236 | static const struct pad_config early_gpio_table[] = { |
Michael Niewöhner | cf2f700 | 2020-12-21 03:46:58 +0100 | [diff] [blame] | 237 | /* C8 : UART0 RX */ |
| 238 | PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), |
| 239 | /* C9 : UART0 TX */ |
| 240 | PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), |
David Wu | a85af8e | 2021-05-13 20:00:09 +0800 | [diff] [blame] | 241 | |
| 242 | /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ |
| 243 | PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), |
| 244 | /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ |
| 245 | /* assert reset on reboot */ |
| 246 | PAD_CFG_GPO(GPP_A13, 0, DEEP), |
| 247 | /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ |
| 248 | PAD_CFG_GPI(GPP_A17, NONE, DEEP), |
| 249 | |
| 250 | /* B2 : VRALERT# ==> EN_PP3300_SSD */ |
| 251 | PAD_CFG_GPO(GPP_B2, 1, DEEP), |
| 252 | /* B11 : PMCALERT# ==> PCH_WP_OD */ |
| 253 | PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), |
| 254 | /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ |
| 255 | PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), |
| 256 | /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ |
| 257 | PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), |
| 258 | /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ |
| 259 | PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), |
| 260 | /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ |
| 261 | PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), |
| 262 | |
| 263 | /* C0 : SMBCLK ==> EN_PP3300_WLAN */ |
| 264 | PAD_CFG_GPO(GPP_C0, 1, DEEP), |
| 265 | /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ |
| 266 | PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), |
| 267 | /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ |
| 268 | PAD_CFG_GPO(GPP_C22, 0, DEEP), |
| 269 | |
| 270 | /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ |
| 271 | PAD_CFG_GPO(GPP_D16, 1, DEEP), |
David Wu | 4cea00a | 2020-04-24 16:13:07 +0800 | [diff] [blame] | 272 | }; |
| 273 | |
| 274 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 275 | { |
| 276 | *num = ARRAY_SIZE(early_gpio_table); |
| 277 | return early_gpio_table; |
| 278 | } |
| 279 | |
Nick Vaccaro | 2f78ce0 | 2021-02-16 19:06:16 -0800 | [diff] [blame] | 280 | /* GPIO settings before entering S5 */ |
| 281 | static const struct pad_config s5_sleep_gpio_table[] = { |
| 282 | PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ |
| 283 | PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ |
| 284 | }; |
| 285 | |
| 286 | const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) |
| 287 | { |
| 288 | if (slp_typ == ACPI_S5) { |
| 289 | *num = ARRAY_SIZE(s5_sleep_gpio_table); |
| 290 | return s5_sleep_gpio_table; |
| 291 | } |
| 292 | *num = 0; |
| 293 | return NULL; |
| 294 | } |
Matt DeVillier | 7ed6130 | 2022-12-21 08:38:17 -0600 | [diff] [blame^] | 295 | |
| 296 | /* GPIOs needed to be set in romstage. */ |
| 297 | static const struct pad_config romstage_gpio_table[] = { |
| 298 | /* Enable touchscreen, hold in reset */ |
| 299 | /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ |
| 300 | PAD_CFG_GPO(GPP_A8, 1, DEEP), |
| 301 | /* C10 : UART0_RTS# ==> USI_RST_L */ |
| 302 | PAD_CFG_GPO(GPP_C10, 0, DEEP), |
| 303 | }; |
| 304 | |
| 305 | const struct pad_config *variant_romstage_gpio_table(size_t *num) |
| 306 | { |
| 307 | *num = ARRAY_SIZE(romstage_gpio_table); |
| 308 | return romstage_gpio_table; |
| 309 | } |