Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | 43b29cf | 2009-03-06 19:11:52 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <stdint.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <device/hypertransport.h> |
| 27 | #include <stdlib.h> |
| 28 | #include <string.h> |
| 29 | #include <bitops.h> |
| 30 | #include <cpu/cpu.h> |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 31 | #include <boot/tables.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 32 | #include "chip.h" |
| 33 | #include "i945.h" |
| 34 | |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 35 | static int get_pcie_bar(u32 *base, u32 *len) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 36 | { |
| 37 | device_t dev; |
| 38 | u32 pciexbar_reg; |
| 39 | |
| 40 | *base = 0; |
| 41 | *len = 0; |
| 42 | |
| 43 | dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 44 | if (!dev) |
| 45 | return 0; |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 46 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 47 | pciexbar_reg = pci_read_config32(dev, PCIEXBAR); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 48 | |
| 49 | if (!(pciexbar_reg & (1 << 0))) |
| 50 | return 0; |
| 51 | |
| 52 | switch ((pciexbar_reg >> 1) & 3) { |
| 53 | case 0: // 256MB |
| 54 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); |
| 55 | *len = 256 * 1024 * 1024; |
| 56 | return 1; |
| 57 | case 1: // 128M |
| 58 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); |
| 59 | *len = 128 * 1024 * 1024; |
| 60 | return 1; |
| 61 | case 2: // 64M |
| 62 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); |
| 63 | *len = 64 * 1024 * 1024; |
| 64 | return 1; |
| 65 | } |
| 66 | |
| 67 | return 0; |
| 68 | } |
| 69 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 70 | /* IDG memory */ |
| 71 | uint64_t uma_memory_base=0, uma_memory_size=0; |
| 72 | |
| 73 | int add_northbridge_resources(struct lb_memory *mem) |
| 74 | { |
| 75 | u32 pcie_config_base, pcie_config_size; |
| 76 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 77 | printk(BIOS_DEBUG, "Adding UMA memory area\n"); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 78 | lb_add_memory_range(mem, LB_MEM_RESERVED, |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 79 | uma_memory_base, uma_memory_size); |
| 80 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 81 | printk(BIOS_DEBUG, "Adding PCIe config bar\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 82 | get_pcie_bar(&pcie_config_base, &pcie_config_size); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 83 | lb_add_memory_range(mem, LB_MEM_RESERVED, |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 84 | pcie_config_base, pcie_config_size); |
| 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 89 | static void ram_resource(device_t dev, unsigned long index, unsigned long basek, |
| 90 | unsigned long sizek) |
| 91 | { |
| 92 | struct resource *resource; |
| 93 | |
| 94 | resource = new_resource(dev, index); |
| 95 | resource->base = ((resource_t) basek) << 10; |
| 96 | resource->size = ((resource_t) sizek) << 10; |
| 97 | resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | |
| 98 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 99 | } |
| 100 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 101 | static void tolm_test(void *gp, struct device *dev, struct resource *new) |
| 102 | { |
| 103 | struct resource **best_p = gp; |
| 104 | struct resource *best; |
| 105 | best = *best_p; |
| 106 | if (!best || (best->base > new->base)) { |
| 107 | best = new; |
| 108 | } |
| 109 | *best_p = best; |
| 110 | } |
| 111 | |
| 112 | static uint32_t find_pci_tolm(struct bus *bus) |
| 113 | { |
| 114 | struct resource *min; |
| 115 | uint32_t tolm; |
| 116 | min = 0; |
| 117 | search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, |
| 118 | &min); |
| 119 | tolm = 0xffffffffUL; |
| 120 | if (min && tolm > min->base) { |
| 121 | tolm = min->base; |
| 122 | } |
| 123 | return tolm; |
| 124 | } |
| 125 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 126 | #if CONFIG_WRITE_HIGH_TABLES==1 |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 127 | #define HIGH_TABLES_SIZE 1024 // maximum size of high tables in KB |
Stefan Reinauer | 3c7f46b | 2009-02-27 23:09:55 +0000 | [diff] [blame] | 128 | extern uint64_t high_tables_base, high_tables_size; |
| 129 | #endif |
Stefan Reinauer | 3c7f46b | 2009-02-27 23:09:55 +0000 | [diff] [blame] | 130 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 131 | static void pci_domain_set_resources(device_t dev) |
| 132 | { |
| 133 | uint32_t pci_tolm; |
| 134 | uint8_t tolud, reg8; |
| 135 | uint16_t reg16; |
Stefan Reinauer | 3c7f46b | 2009-02-27 23:09:55 +0000 | [diff] [blame] | 136 | unsigned long long tomk; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 137 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 138 | /* Can we find out how much memory we can use at most |
| 139 | * this way? |
| 140 | */ |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 141 | pci_tolm = find_pci_tolm(dev->link_list); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 142 | printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 143 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 144 | printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n", |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 145 | pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c)); |
| 146 | |
| 147 | tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 148 | printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 149 | |
| 150 | tomk = tolud << 14; |
| 151 | |
| 152 | /* Note: subtract IGD device and TSEG */ |
| 153 | reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e); |
| 154 | if (reg8 & 1) { |
| 155 | int tseg_size = 0; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 156 | printk(BIOS_DEBUG, "TSEG decoded, subtracting "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 157 | reg8 >>= 1; |
| 158 | reg8 &= 3; |
| 159 | switch (reg8) { |
| 160 | case 0: |
| 161 | tseg_size = 1024; |
Stefan Reinauer | 3c7f46b | 2009-02-27 23:09:55 +0000 | [diff] [blame] | 162 | break; /* TSEG = 1M */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 163 | case 1: |
| 164 | tseg_size = 2048; |
Stefan Reinauer | 3c7f46b | 2009-02-27 23:09:55 +0000 | [diff] [blame] | 165 | break; /* TSEG = 2M */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 166 | case 2: |
| 167 | tseg_size = 8192; |
Stefan Reinauer | 3c7f46b | 2009-02-27 23:09:55 +0000 | [diff] [blame] | 168 | break; /* TSEG = 8M */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 169 | } |
| 170 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 171 | printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 172 | tomk -= tseg_size; |
| 173 | } |
| 174 | |
| 175 | reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); |
| 176 | if (!(reg16 & 2)) { |
| 177 | int uma_size = 0; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 178 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 179 | reg16 >>= 4; |
| 180 | reg16 &= 7; |
| 181 | switch (reg16) { |
| 182 | case 1: |
| 183 | uma_size = 1024; |
| 184 | break; |
| 185 | case 3: |
| 186 | uma_size = 8192; |
| 187 | break; |
| 188 | } |
| 189 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 190 | printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 191 | tomk -= uma_size; |
Stefan Reinauer | 3c7f46b | 2009-02-27 23:09:55 +0000 | [diff] [blame] | 192 | |
| 193 | /* For reserving UMA memory in the memory map */ |
| 194 | uma_memory_base = tomk * 1024ULL; |
| 195 | uma_memory_size = uma_size * 1024ULL; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | /* The following needs to be 2 lines, otherwise the second |
| 199 | * number is always 0 |
| 200 | */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 201 | printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk); |
| 202 | printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 203 | |
| 204 | /* Report the memory regions */ |
| 205 | ram_resource(dev, 3, 0, 640); |
Stefan Reinauer | 3c7f46b | 2009-02-27 23:09:55 +0000 | [diff] [blame] | 206 | ram_resource(dev, 4, 768, (tomk - 768)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 207 | if (tomk > 4 * 1024 * 1024) { |
| 208 | ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); |
| 209 | } |
| 210 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 211 | assign_resources(dev->link_list); |
Stefan Reinauer | 3c7f46b | 2009-02-27 23:09:55 +0000 | [diff] [blame] | 212 | |
Myles Watson | b8e2027 | 2009-10-15 13:35:47 +0000 | [diff] [blame] | 213 | #if CONFIG_WRITE_HIGH_TABLES==1 |
Stefan Reinauer | 3c7f46b | 2009-02-27 23:09:55 +0000 | [diff] [blame] | 214 | /* Leave some space for ACPI, PIRQ and MP tables */ |
| 215 | high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; |
| 216 | high_tables_size = HIGH_TABLES_SIZE * 1024; |
| 217 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 218 | } |
| 219 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 220 | /* TODO We could determine how many PCIe busses we need in |
| 221 | * the bar. For now that number is hardcoded to a max of 64. |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 222 | * See e7525/northbridge.c for an example. |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 223 | */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 224 | static struct device_operations pci_domain_ops = { |
| 225 | .read_resources = pci_domain_read_resources, |
| 226 | .set_resources = pci_domain_set_resources, |
| 227 | .enable_resources = enable_childrens_resources, |
| 228 | .init = 0, |
| 229 | .scan_bus = pci_domain_scan_bus, |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 230 | #if CONFIG_MMCONF_SUPPORT_DEFAULT |
Stefan Reinauer | 43b29cf | 2009-03-06 19:11:52 +0000 | [diff] [blame] | 231 | .ops_pci_bus = &pci_ops_mmconf, |
| 232 | #else |
| 233 | .ops_pci_bus = &pci_cf8_conf1, |
| 234 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 235 | }; |
| 236 | |
| 237 | static void mc_read_resources(device_t dev) |
| 238 | { |
| 239 | struct resource *resource; |
| 240 | |
| 241 | pci_dev_read_resources(dev); |
| 242 | |
| 243 | /* So, this is one of the big mysteries in the coreboot resource |
| 244 | * allocator. This resource should make sure that the address space |
| 245 | * of the PCIe memory mapped config space bar. But it does not. |
| 246 | */ |
| 247 | |
| 248 | /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ |
| 249 | resource = new_resource(dev, 0xcf); |
| 250 | resource->base = DEFAULT_PCIEXBAR; |
| 251 | resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ |
| 252 | resource->flags = |
| 253 | IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 254 | IORESOURCE_ASSIGNED; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 255 | printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 256 | (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | static void mc_set_resources(device_t dev) |
| 260 | { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 261 | struct resource *resource; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 262 | |
| 263 | /* Report the PCIe BAR */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 264 | resource = find_resource(dev, 0xcf); |
| 265 | if (resource) { |
| 266 | report_resource_stored(dev, resource, "<mmconfig>"); |
| 267 | } |
| 268 | |
| 269 | /* And call the normal set_resources */ |
| 270 | pci_dev_set_resources(dev); |
| 271 | } |
| 272 | |
| 273 | static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 274 | { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 275 | if (!vendor || !device) { |
| 276 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 277 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 278 | } else { |
| 279 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 280 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 281 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 282 | } |
| 283 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 284 | #if CONFIG_HAVE_ACPI_RESUME |
| 285 | extern u8 acpi_slp_type; |
| 286 | |
| 287 | static void northbridge_init(struct device *dev) |
| 288 | { |
| 289 | switch (pci_read_config32(dev, SKPAD)) { |
| 290 | case 0xcafebabe: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 291 | printk(BIOS_DEBUG, "Normal boot.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 292 | acpi_slp_type=0; |
| 293 | break; |
| 294 | case 0xcafed00d: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 295 | printk(BIOS_DEBUG, "S3 Resume.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 296 | acpi_slp_type=3; |
| 297 | break; |
| 298 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 299 | printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 300 | acpi_slp_type=0; |
| 301 | break; |
| 302 | } |
| 303 | } |
| 304 | #endif |
| 305 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 306 | static struct pci_operations intel_pci_ops = { |
| 307 | .set_subsystem = intel_set_subsystem, |
| 308 | }; |
| 309 | |
| 310 | static struct device_operations mc_ops = { |
| 311 | .read_resources = mc_read_resources, |
| 312 | .set_resources = mc_set_resources, |
| 313 | .enable_resources = pci_dev_enable_resources, |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 314 | #if CONFIG_HAVE_ACPI_RESUME |
| 315 | .init = northbridge_init, |
| 316 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 317 | .scan_bus = 0, |
| 318 | .ops_pci = &intel_pci_ops, |
| 319 | }; |
| 320 | |
| 321 | static const struct pci_driver mc_driver __pci_driver = { |
| 322 | .ops = &mc_ops, |
| 323 | .vendor = PCI_VENDOR_ID_INTEL, |
Uwe Hermann | 5d7a1c8 | 2008-10-31 18:41:09 +0000 | [diff] [blame] | 324 | .device = 0x27a0, |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 325 | }; |
| 326 | |
| 327 | static void cpu_bus_init(device_t dev) |
| 328 | { |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 329 | initialize_cpus(dev->link_list); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 330 | } |
| 331 | |
| 332 | static void cpu_bus_noop(device_t dev) |
| 333 | { |
| 334 | } |
| 335 | |
| 336 | static struct device_operations cpu_bus_ops = { |
| 337 | .read_resources = cpu_bus_noop, |
| 338 | .set_resources = cpu_bus_noop, |
| 339 | .enable_resources = cpu_bus_noop, |
| 340 | .init = cpu_bus_init, |
| 341 | .scan_bus = 0, |
| 342 | }; |
| 343 | |
| 344 | static void enable_dev(device_t dev) |
| 345 | { |
| 346 | /* Set the operations if it is a special bus type */ |
| 347 | if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { |
| 348 | dev->ops = &pci_domain_ops; |
| 349 | } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { |
| 350 | dev->ops = &cpu_bus_ops; |
| 351 | } |
| 352 | } |
| 353 | |
| 354 | struct chip_operations northbridge_intel_i945_ops = { |
| 355 | CHIP_NAME("Intel i945 Northbridge") |
| 356 | .enable_dev = enable_dev, |
| 357 | }; |