Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <stdint.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <device/hypertransport.h> |
| 27 | #include <stdlib.h> |
| 28 | #include <string.h> |
| 29 | #include <bitops.h> |
| 30 | #include <cpu/cpu.h> |
| 31 | #include "chip.h" |
| 32 | #include "i945.h" |
| 33 | |
| 34 | static void ram_resource(device_t dev, unsigned long index, unsigned long basek, |
| 35 | unsigned long sizek) |
| 36 | { |
| 37 | struct resource *resource; |
| 38 | |
| 39 | resource = new_resource(dev, index); |
| 40 | resource->base = ((resource_t) basek) << 10; |
| 41 | resource->size = ((resource_t) sizek) << 10; |
| 42 | resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | |
| 43 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 44 | } |
| 45 | |
| 46 | static void pci_domain_read_resources(device_t dev) |
| 47 | { |
| 48 | struct resource *resource; |
| 49 | |
| 50 | /* Initialize the system wide io space constraints */ |
| 51 | resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
| 52 | resource->base = 0; |
| 53 | resource->size = 0; |
| 54 | resource->align = 0; |
| 55 | resource->gran = 0; |
| 56 | resource->limit = 0xffffUL; |
| 57 | resource->flags = |
| 58 | IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; |
| 59 | |
| 60 | /* Initialize the system wide memory resources constraints */ |
| 61 | resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
| 62 | resource->base = 0; |
| 63 | resource->size = 0; |
| 64 | resource->align = 0; |
| 65 | resource->gran = 0; |
| 66 | resource->limit = 0xffffffffUL; |
| 67 | resource->flags = |
| 68 | IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; |
| 69 | } |
| 70 | |
| 71 | static void tolm_test(void *gp, struct device *dev, struct resource *new) |
| 72 | { |
| 73 | struct resource **best_p = gp; |
| 74 | struct resource *best; |
| 75 | best = *best_p; |
| 76 | if (!best || (best->base > new->base)) { |
| 77 | best = new; |
| 78 | } |
| 79 | *best_p = best; |
| 80 | } |
| 81 | |
| 82 | static uint32_t find_pci_tolm(struct bus *bus) |
| 83 | { |
| 84 | struct resource *min; |
| 85 | uint32_t tolm; |
| 86 | min = 0; |
| 87 | search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, |
| 88 | &min); |
| 89 | tolm = 0xffffffffUL; |
| 90 | if (min && tolm > min->base) { |
| 91 | tolm = min->base; |
| 92 | } |
| 93 | return tolm; |
| 94 | } |
| 95 | |
| 96 | static void pci_domain_set_resources(device_t dev) |
| 97 | { |
| 98 | uint32_t pci_tolm; |
| 99 | uint8_t tolud, reg8; |
| 100 | uint16_t reg16; |
| 101 | unsigned long long tomk, tolmk; |
| 102 | |
| 103 | pci_tolm = find_pci_tolm(&dev->link[0]); |
| 104 | |
| 105 | printk_spew("Base of stolen memory: 0x%08x\n", |
| 106 | pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c)); |
| 107 | |
| 108 | tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c); |
| 109 | printk_spew("Top of Low Used DRAM: 0x%08x\n", tolud << 24); |
| 110 | |
| 111 | tomk = tolud << 14; |
| 112 | |
| 113 | /* Note: subtract IGD device and TSEG */ |
| 114 | reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e); |
| 115 | if (reg8 & 1) { |
| 116 | int tseg_size = 0; |
| 117 | printk_debug("TSEG decoded, subtracting "); |
| 118 | reg8 >>= 1; |
| 119 | reg8 &= 3; |
| 120 | switch (reg8) { |
| 121 | case 0: |
| 122 | tseg_size = 1024; |
| 123 | break; |
| 124 | case 1: |
| 125 | tseg_size = 2048; |
| 126 | break; |
| 127 | case 2: |
| 128 | tseg_size = 8192; |
| 129 | break; |
| 130 | } |
| 131 | |
| 132 | printk_debug("%dM\n", tseg_size >> 10); |
| 133 | tomk -= tseg_size; |
| 134 | } |
| 135 | |
| 136 | reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); |
| 137 | if (!(reg16 & 2)) { |
| 138 | int uma_size = 0; |
| 139 | printk_debug("IGD decoded, subtracting "); |
| 140 | reg16 >>= 4; |
| 141 | reg16 &= 7; |
| 142 | switch (reg16) { |
| 143 | case 1: |
| 144 | uma_size = 1024; |
| 145 | break; |
| 146 | case 3: |
| 147 | uma_size = 8192; |
| 148 | break; |
| 149 | } |
| 150 | |
| 151 | printk_debug("%dM UMA\n", uma_size >> 10); |
| 152 | tomk -= uma_size; |
| 153 | } |
| 154 | |
| 155 | /* The following needs to be 2 lines, otherwise the second |
| 156 | * number is always 0 |
| 157 | */ |
| 158 | printk_info("Available memory: %dK", tomk); |
| 159 | printk_info(" (%dM)\n", (tomk >> 10)); |
| 160 | |
| 161 | tolmk = tomk; |
| 162 | |
| 163 | /* Report the memory regions */ |
| 164 | ram_resource(dev, 3, 0, 640); |
| 165 | ram_resource(dev, 4, 768, (tolmk - 768)); |
| 166 | if (tomk > 4 * 1024 * 1024) { |
| 167 | ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); |
| 168 | } |
| 169 | |
| 170 | assign_resources(&dev->link[0]); |
| 171 | } |
| 172 | |
| 173 | static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) |
| 174 | { |
| 175 | max = pci_scan_bus(&dev->link[0], 0, 0xff, max); |
| 176 | /* TODO We could determine how many PCIe busses we need in |
| 177 | * the bar. For now that number is hardcoded to a max of 64. |
| 178 | */ |
| 179 | return max; |
| 180 | } |
| 181 | |
| 182 | static struct device_operations pci_domain_ops = { |
| 183 | .read_resources = pci_domain_read_resources, |
| 184 | .set_resources = pci_domain_set_resources, |
| 185 | .enable_resources = enable_childrens_resources, |
| 186 | .init = 0, |
| 187 | .scan_bus = pci_domain_scan_bus, |
| 188 | .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ |
| 189 | }; |
| 190 | |
| 191 | static void mc_read_resources(device_t dev) |
| 192 | { |
| 193 | struct resource *resource; |
| 194 | |
| 195 | pci_dev_read_resources(dev); |
| 196 | |
| 197 | /* So, this is one of the big mysteries in the coreboot resource |
| 198 | * allocator. This resource should make sure that the address space |
| 199 | * of the PCIe memory mapped config space bar. But it does not. |
| 200 | */ |
| 201 | |
| 202 | /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ |
| 203 | resource = new_resource(dev, 0xcf); |
| 204 | resource->base = DEFAULT_PCIEXBAR; |
| 205 | resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ |
| 206 | resource->flags = |
| 207 | IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 208 | IORESOURCE_ASSIGNED; |
| 209 | printk_debug("Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n", |
| 210 | resource->base, (resource->base + resource->size)); |
| 211 | } |
| 212 | |
| 213 | static void mc_set_resources(device_t dev) |
| 214 | { |
| 215 | struct resource *resource, *last; |
| 216 | |
| 217 | /* Report the PCIe BAR */ |
| 218 | last = &dev->resource[dev->resources]; |
| 219 | resource = find_resource(dev, 0xcf); |
| 220 | if (resource) { |
| 221 | report_resource_stored(dev, resource, "<mmconfig>"); |
| 222 | } |
| 223 | |
| 224 | /* And call the normal set_resources */ |
| 225 | pci_dev_set_resources(dev); |
| 226 | } |
| 227 | |
| 228 | static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 229 | { |
| 230 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 231 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 232 | } |
| 233 | |
| 234 | static struct pci_operations intel_pci_ops = { |
| 235 | .set_subsystem = intel_set_subsystem, |
| 236 | }; |
| 237 | |
| 238 | static struct device_operations mc_ops = { |
| 239 | .read_resources = mc_read_resources, |
| 240 | .set_resources = mc_set_resources, |
| 241 | .enable_resources = pci_dev_enable_resources, |
| 242 | .init = 0, |
| 243 | .scan_bus = 0, |
| 244 | .ops_pci = &intel_pci_ops, |
| 245 | }; |
| 246 | |
| 247 | static const struct pci_driver mc_driver __pci_driver = { |
| 248 | .ops = &mc_ops, |
| 249 | .vendor = PCI_VENDOR_ID_INTEL, |
Uwe Hermann | 5d7a1c8 | 2008-10-31 18:41:09 +0000 | [diff] [blame^] | 250 | .device = 0x27a0, |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 251 | }; |
| 252 | |
| 253 | static void cpu_bus_init(device_t dev) |
| 254 | { |
| 255 | initialize_cpus(&dev->link[0]); |
| 256 | } |
| 257 | |
| 258 | static void cpu_bus_noop(device_t dev) |
| 259 | { |
| 260 | } |
| 261 | |
| 262 | static struct device_operations cpu_bus_ops = { |
| 263 | .read_resources = cpu_bus_noop, |
| 264 | .set_resources = cpu_bus_noop, |
| 265 | .enable_resources = cpu_bus_noop, |
| 266 | .init = cpu_bus_init, |
| 267 | .scan_bus = 0, |
| 268 | }; |
| 269 | |
| 270 | static void enable_dev(device_t dev) |
| 271 | { |
| 272 | /* Set the operations if it is a special bus type */ |
| 273 | if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { |
| 274 | dev->ops = &pci_domain_ops; |
| 275 | } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { |
| 276 | dev->ops = &cpu_bus_ops; |
| 277 | } |
| 278 | } |
| 279 | |
| 280 | struct chip_operations northbridge_intel_i945_ops = { |
| 281 | CHIP_NAME("Intel i945 Northbridge") |
| 282 | .enable_dev = enable_dev, |
| 283 | }; |