Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame^] | 2 | * This file is part of the coreboot project. |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2004 Tyan Computer |
| 5 | * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. |
| 6 | * Copyright (C) 2006,2007 AMD |
| 7 | * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. |
| 8 | * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) |
| 9 | * Written by Morgan Tsai <my_tsai@sis.com> for SiS. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 24 | */ |
| 25 | |
| 26 | #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE |
| 27 | #define SIS966_DEVN_BASE HT_CHAIN_END_UNITID_BASE |
| 28 | #else |
| 29 | #define SIS966_DEVN_BASE HT_CHAIN_UNITID_BASE |
| 30 | #endif |
| 31 | |
| 32 | static void sis966_enable_rom(void) |
| 33 | { |
| 34 | device_t addr; |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 35 | |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 36 | /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ |
| 37 | addr = pci_locate_device(PCI_ID(0x1039, 0x0966), 0); |
| 38 | |
| 39 | /* Set the 4MB enable bit bit */ |
| 40 | pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11); |
| 41 | } |