Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame^] | 2 | * This file is part of the coreboot project. |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 19 | |
| 20 | #include <arch/pirq_routing.h> |
| 21 | #include <console/console.h> |
| 22 | #include <arch/io.h> |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 23 | #include "../../../southbridge/amd/cs5536/cs5536.h" |
| 24 | |
| 25 | /* Platform IRQs */ |
| 26 | #define PIRQA 11 |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 27 | #define PIRQB 10 |
| 28 | #define PIRQC 11 |
| 29 | #define PIRQD 9 |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 30 | |
| 31 | /* Map */ |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 32 | #define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ |
| 33 | #define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ |
| 34 | #define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ |
| 35 | #define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 36 | |
| 37 | /* Link */ |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 38 | #define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ |
| 39 | #define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ |
| 40 | #define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ |
| 41 | #define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 42 | |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 43 | /* |
| 44 | * ALIX1.C interrupt wiring. |
| 45 | * |
| 46 | * Devices are: |
| 47 | * |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 48 | * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31) |
| 49 | * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block |
| 50 | * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) |
| 51 | * 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01) |
| 52 | * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) |
| 53 | * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) |
| 54 | * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01) |
| 55 | * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) |
| 56 | * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 57 | * |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 58 | * The only devices that interrupt are: |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 59 | * |
| 60 | * What Device IRQ PIN PIN WIRED TO |
| 61 | * ------------------------------------------------- |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 62 | * AES 00:01.2 0a 01 A A |
| 63 | * 3VPCI 00:0c.0 0a 01 A A |
| 64 | * eth0 00:0d.0 0b 01 A B |
| 65 | * mpci 00:0e.0 0a 01 A A |
| 66 | * usb 00:0f.3 0b 02 B B |
| 67 | * usb 00:0f.4 0b 04 D D |
| 68 | * usb 00:0f.5 0b 04 D D |
| 69 | * |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 70 | * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B. |
| 71 | */ |
| 72 | |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 73 | const struct irq_routing_table intel_irq_routing_table = { |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 74 | PIRQ_SIGNATURE, |
| 75 | PIRQ_VERSION, |
| 76 | 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ |
| 77 | 0x00, /* Where the interrupt router lies (bus) */ |
| 78 | (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ |
| 79 | 0x00, /* IRQs devoted exclusively to PCI usage */ |
| 80 | 0x100B, /* Vendor */ |
| 81 | 0x002B, /* Device */ |
| 82 | 0, /* Crap (miniport) */ |
| 83 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ |
| 84 | 0x00, /* Checksum */ |
| 85 | { |
| 86 | /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ |
| 87 | |
| 88 | /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ |
| 89 | |
| 90 | /* CPU */ |
| 91 | {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, |
| 92 | |
| 93 | /* PCI (slot 1) */ |
Ronald G. Minnich | 254f47e | 2007-11-26 21:43:21 +0000 | [diff] [blame] | 94 | {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x4, 0x0}, |
Uwe Hermann | 8b942e7 | 2007-11-13 16:24:15 +0000 | [diff] [blame] | 95 | |
| 96 | /* On-board ethernet */ |
| 97 | {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, |
| 98 | |
| 99 | /* Mini PCI (slot 2) */ |
| 100 | {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, |
| 101 | |
| 102 | /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ |
| 103 | {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 104 | } |
| 105 | }; |
| 106 | |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 107 | unsigned long write_pirq_routing_table(unsigned long addr) |
| 108 | { |
| 109 | int i, j, k, num_entries; |
| 110 | unsigned char pirq[4]; |
| 111 | uint16_t chipset_irq_map; |
| 112 | uint32_t pciAddr, pirtable_end; |
| 113 | struct irq_routing_table *pirq_tbl; |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 114 | |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 115 | pirtable_end = copy_pirq_routing_table(addr); |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 116 | |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 117 | /* Set up chipset IRQ steering. */ |
| 118 | pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; |
| 119 | chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); |
| 120 | printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, |
| 121 | chipset_irq_map); |
| 122 | outl(pciAddr & ~3, 0xCF8); |
| 123 | outl(chipset_irq_map, 0xCFC); |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 124 | |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 125 | pirq_tbl = (struct irq_routing_table *) (addr); |
| 126 | num_entries = (pirq_tbl->size - 32) / 16; |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 127 | |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 128 | /* Set PCI IRQs. */ |
| 129 | for (i = 0; i < num_entries; i++) { |
| 130 | printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, |
| 131 | pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); |
| 132 | for (j = 0; j < 4; j++) { |
| 133 | printk_debug("INT: %c bitmap: %x ", 'A' + j, |
| 134 | pirq_tbl->slots[i].irq[j].bitmap); |
| 135 | /* Finds lsb in bitmap to IRQ#. */ |
| 136 | for (k = 0; |
| 137 | (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) |
| 138 | && (pirq_tbl->slots[i].irq[j].bitmap != 0); |
| 139 | k++); |
| 140 | pirq[j] = k; |
| 141 | printk_debug("PIRQ: %d\n", k); |
| 142 | } |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 143 | |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 144 | /* Bus, device, slots IRQs for {A,B,C,D}. */ |
| 145 | pci_assign_irqs(pirq_tbl->slots[i].bus, |
| 146 | pirq_tbl->slots[i].devfn >> 3, pirq); |
| 147 | } |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 148 | |
Ronald G. Minnich | 6503cd9 | 2007-11-07 23:13:43 +0000 | [diff] [blame] | 149 | /* Put the PIR table in memory and checksum. */ |
| 150 | return pirtable_end; |
Ronald G. Minnich | 6226f13 | 2007-09-08 18:32:53 +0000 | [diff] [blame] | 151 | } |