Marc Jones | bd88057 | 2007-06-12 22:54:41 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame^] | 2 | * This file is part of the coreboot project. |
Marc Jones | bd88057 | 2007-06-12 22:54:41 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/pirq_routing.h> |
| 21 | #include <console/console.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <arch/pirq_routing.h> |
| 24 | #include "../../../southbridge/amd/cs5536/cs5536.h" |
| 25 | |
| 26 | /* Platform IRQs */ |
| 27 | #define PIRQA 10 |
| 28 | #define PIRQB 11 |
| 29 | #define PIRQC 10 |
| 30 | #define PIRQD 11 |
| 31 | |
| 32 | /* Map */ |
| 33 | #define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ |
| 34 | #define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ |
| 35 | #define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ |
| 36 | #define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ |
| 37 | |
| 38 | /* Link */ |
| 39 | #define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ |
| 40 | #define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ |
| 41 | #define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ |
| 42 | #define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ |
| 43 | |
| 44 | const struct irq_routing_table intel_irq_routing_table = { |
| 45 | PIRQ_SIGNATURE, /* u32 signature */ |
| 46 | PIRQ_VERSION, /* u16 version */ |
| 47 | 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ |
| 48 | 0x00, /* Where the interrupt router lies (bus) */ |
| 49 | (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ |
| 50 | 0x00, /* IRQs devoted exclusively to PCI usage */ |
| 51 | 0x100B, /* Vendor */ |
| 52 | 0x002B, /* Device */ |
| 53 | 0, /* Crap (miniport) */ |
| 54 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ |
| 55 | 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ |
| 56 | { |
| 57 | /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ |
| 58 | /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ |
| 59 | {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ |
| 60 | {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ |
| 61 | {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ |
| 62 | {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */ |
| 63 | } |
| 64 | }; |
| 65 | |
| 66 | unsigned long write_pirq_routing_table(unsigned long addr) |
| 67 | { |
| 68 | int i, j, k, num_entries; |
| 69 | unsigned char pirq[4]; |
| 70 | uint16_t chipset_irq_map; |
| 71 | uint32_t pciAddr, pirtable_end; |
| 72 | struct irq_routing_table *pirq_tbl; |
| 73 | |
| 74 | pirtable_end = copy_pirq_routing_table(addr); |
| 75 | |
| 76 | /* Set up chipset IRQ steering. */ |
| 77 | pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; |
| 78 | chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); |
| 79 | printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, |
| 80 | chipset_irq_map); |
| 81 | outl(pciAddr & ~3, 0xCF8); |
| 82 | outl(chipset_irq_map, 0xCFC); |
| 83 | |
| 84 | pirq_tbl = (struct irq_routing_table *)(addr); |
| 85 | num_entries = (pirq_tbl->size - 32) / 16; |
| 86 | |
| 87 | /* Set PCI IRQs. */ |
| 88 | for (i = 0; i < num_entries; i++) { |
| 89 | printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, |
| 90 | pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); |
| 91 | for (j = 0; j < 4; j++) { |
| 92 | printk_debug("INT: %c bitmap: %x ", 'A' + j, |
| 93 | pirq_tbl->slots[i].irq[j].bitmap); |
| 94 | for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */ |
| 95 | pirq[j] = k; |
| 96 | printk_debug("PIRQ: %d\n", k); |
| 97 | } |
| 98 | |
| 99 | /* Bus, device, slots IRQs for {A,B,C,D}. */ |
| 100 | pci_assign_irqs(pirq_tbl->slots[i].bus, |
| 101 | pirq_tbl->slots[i].devfn >> 3, pirq); |
| 102 | } |
| 103 | |
| 104 | /* Put the PIR table in memory and checksum. */ |
| 105 | return pirtable_end; |
| 106 | } |