zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame^] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Gnb fuse table |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. |
| 19 | * |
| 20 | * AMD is granting you permission to use this software (the Materials) |
| 21 | * pursuant to the terms and conditions of your Software License Agreement |
| 22 | * with AMD. This header does *NOT* give you permission to use the Materials |
| 23 | * or any rights under AMD's intellectual property. Your use of any portion |
| 24 | * of these Materials shall constitute your acceptance of those terms and |
| 25 | * conditions. If you do not agree to the terms and conditions of the Software |
| 26 | * License Agreement, please do not use any portion of these Materials. |
| 27 | * |
| 28 | * CONFIDENTIALITY: The Materials and all other information, identified as |
| 29 | * confidential and provided to you by AMD shall be kept confidential in |
| 30 | * accordance with the terms and conditions of the Software License Agreement. |
| 31 | * |
| 32 | * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION |
| 33 | * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED |
| 34 | * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF |
| 35 | * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, |
| 36 | * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. |
| 37 | * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER |
| 38 | * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS |
| 39 | * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, |
| 40 | * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER |
| 41 | * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF |
| 42 | * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE |
| 43 | * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, |
| 44 | * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. |
| 45 | * |
| 46 | * AMD does not assume any responsibility for any errors which may appear in |
| 47 | * the Materials or any other related information provided to you by AMD, or |
| 48 | * result from use of the Materials or any related information. |
| 49 | * |
| 50 | * You agree that you will not reverse engineer or decompile the Materials. |
| 51 | * |
| 52 | * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any |
| 53 | * further information, software, technical information, know-how, or show-how |
| 54 | * available to you. Additionally, AMD retains the right to modify the |
| 55 | * Materials at any time, without notice, and is not obligated to provide such |
| 56 | * modified Materials to you. |
| 57 | * |
| 58 | * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with |
| 59 | * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is |
| 60 | * subject to the restrictions as set forth in FAR 52.227-14 and |
| 61 | * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the |
| 62 | * Government constitutes acknowledgement of AMD's proprietary rights in them. |
| 63 | * |
| 64 | * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any |
| 65 | * direct product thereof will be exported directly or indirectly, into any |
| 66 | * country prohibited by the United States Export Administration Act and the |
| 67 | * regulations thereunder, without the required authorization from the U.S. |
| 68 | * government nor will be used for any purpose prohibited by the same. |
| 69 | * *************************************************************************** |
| 70 | * |
| 71 | */ |
| 72 | |
| 73 | /*---------------------------------------------------------------------------------------- |
| 74 | * M O D U L E S U S E D |
| 75 | *---------------------------------------------------------------------------------------- |
| 76 | */ |
| 77 | |
| 78 | #include "AGESA.h" |
| 79 | #include "Ids.h" |
| 80 | #include "amdlib.h" |
| 81 | #include "heapManager.h" |
| 82 | #include "Gnb.h" |
| 83 | #include "GnbGfxFamServices.h" |
| 84 | #include "GnbCommonLib.h" |
| 85 | #include "GnbFuseTable.h" |
| 86 | #include "GnbFuseTableTN.h" |
| 87 | #include "GnbRegistersTN.h" |
| 88 | #include "GnbRegisterAccTN.h" |
| 89 | #include "OptionGnb.h" |
| 90 | #include "Filecode.h" |
| 91 | #define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE |
| 92 | /*---------------------------------------------------------------------------------------- |
| 93 | * D E F I N I T I O N S A N D M A C R O S |
| 94 | *---------------------------------------------------------------------------------------- |
| 95 | */ |
| 96 | |
| 97 | extern GNB_BUILD_OPTIONS GnbBuildOptions; |
| 98 | |
| 99 | /*---------------------------------------------------------------------------------------- |
| 100 | * T Y P E D E F S A N D S T R U C T U R E S |
| 101 | *---------------------------------------------------------------------------------------- |
| 102 | */ |
| 103 | |
| 104 | |
| 105 | |
| 106 | /*---------------------------------------------------------------------------------------- |
| 107 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 108 | *---------------------------------------------------------------------------------------- |
| 109 | */ |
| 110 | |
| 111 | VOID |
| 112 | GnbFuseTableDebugDumpTN ( |
| 113 | IN PP_FUSE_ARRAY *PpFuseArray, |
| 114 | IN AMD_CONFIG_PARAMS *StdHeader |
| 115 | ); |
| 116 | |
| 117 | |
| 118 | |
| 119 | PP_FUSE_ARRAY ex907 = { |
| 120 | 0, // PP table revision |
| 121 | {1, 0, 0, 0, 0, 0}, // Valid DPM states |
| 122 | {0x40, 0, 0, 0, 0, 0}, // Sclk DPM DID |
| 123 | {0, 0, 0, 0, 0, 0}, // Sclk DPM VID |
| 124 | {0, 0, 0, 0, 0}, // Sclk DPM Cac |
| 125 | {1, 0, 0, 0, 0, 0}, // State policy flags |
| 126 | {2, 0, 0, 0, 0, 0}, // State policy label |
| 127 | {0x40, 0, 0, 0}, // VCLK DID |
| 128 | {0x40, 0, 0, 0}, // DCLK DID |
| 129 | 8, // Thermal SCLK |
| 130 | {0, 0, 0, 0, 0, 0}, // Vclk/Dclk selector |
| 131 | {0, 0, 0, 0}, // Valid Lclk DPM states |
| 132 | {0x40, 0x40, 0x40, 0}, // Lclk DPM DID |
| 133 | {0x40, 0x40, 0x40, 0}, // Lclk DPM VID |
| 134 | {0, 0, 0, 0}, // Displclk DID |
| 135 | 3, // Pcie Gen 2 VID |
| 136 | 0x10, // Main PLL id for 3200 VCO |
| 137 | 0, // WRCK SMU clock Divisor |
| 138 | {0x24, 0x24, 0x24, 0x24}, // SCLK VID |
| 139 | 0, // GPU boost cap |
| 140 | {0, 0, 0, 0, 0, 0}, // Sclk DPM TDP limit |
| 141 | 0, // TDP limit PG |
| 142 | 0, // Boost margin |
| 143 | 0, // Throttle margin |
| 144 | TRUE, // Support VCE in PP table |
| 145 | {0x3, 0xC, 0x30, 0xC0}, // VCE Flags |
| 146 | {0, 1, 0, 1}, // MCLK for VCE |
| 147 | {0, 0, 0, 0}, // SCLK selector for VCE |
| 148 | {0x40, 0x40, 0x40, 0x40} // Eclk DID |
| 149 | }; |
| 150 | |
| 151 | |
| 152 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104158_TABLE [] = { |
| 153 | { |
| 154 | D0F0xBC_xE0104158_EClkDid0_OFFSET, |
| 155 | D0F0xBC_xE0104158_EClkDid0_WIDTH, |
| 156 | (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[0]) |
| 157 | }, |
| 158 | { |
| 159 | D0F0xBC_xE0104158_EClkDid1_OFFSET, |
| 160 | D0F0xBC_xE0104158_EClkDid1_WIDTH, |
| 161 | (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[1]) |
| 162 | }, |
| 163 | { |
| 164 | D0F0xBC_xE0104158_EClkDid2_OFFSET, |
| 165 | D0F0xBC_xE0104158_EClkDid2_WIDTH, |
| 166 | (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[2]) |
| 167 | } |
| 168 | }; |
| 169 | |
| 170 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010415B_TABLE [] = { |
| 171 | { |
| 172 | D0F0xBC_xE010415B_EClkDid3_OFFSET, |
| 173 | D0F0xBC_xE010415B_EClkDid3_WIDTH, |
| 174 | (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[3]) |
| 175 | } |
| 176 | }; |
| 177 | |
| 178 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104184_TABLE [] = { |
| 179 | { |
| 180 | D0F0xBC_xE0104184_VCEFlag0_OFFSET, |
| 181 | D0F0xBC_xE0104184_VCEFlag0_WIDTH, |
| 182 | (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[0]) |
| 183 | }, |
| 184 | { |
| 185 | D0F0xBC_xE0104184_VCEFlag1_OFFSET, |
| 186 | D0F0xBC_xE0104184_VCEFlag1_WIDTH, |
| 187 | (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[1]) |
| 188 | } |
| 189 | }; |
| 190 | |
| 191 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104187_TABLE [] = { |
| 192 | { |
| 193 | D0F0xBC_xE0104187_VCEFlag2_OFFSET, |
| 194 | D0F0xBC_xE0104187_VCEFlag2_WIDTH, |
| 195 | (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[2]) |
| 196 | } |
| 197 | }; |
| 198 | |
| 199 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104188_TABLE [] = { |
| 200 | { |
| 201 | D0F0xBC_xE0104188_VCEFlag3_OFFSET, |
| 202 | D0F0xBC_xE0104188_VCEFlag3_WIDTH, |
| 203 | (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[3]) |
| 204 | }, |
| 205 | { |
| 206 | D0F0xBC_xE0104188_ReqSclkSel0_OFFSET, |
| 207 | D0F0xBC_xE0104188_ReqSclkSel0_WIDTH, |
| 208 | (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[0]) |
| 209 | }, |
| 210 | { |
| 211 | D0F0xBC_xE0104188_ReqSclkSel1_OFFSET, |
| 212 | D0F0xBC_xE0104188_ReqSclkSel1_WIDTH, |
| 213 | (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[1]) |
| 214 | }, |
| 215 | { |
| 216 | D0F0xBC_xE0104188_ReqSclkSel2_OFFSET, |
| 217 | D0F0xBC_xE0104188_ReqSclkSel2_WIDTH, |
| 218 | (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[2]) |
| 219 | }, |
| 220 | { |
| 221 | D0F0xBC_xE0104188_ReqSclkSel3_OFFSET, |
| 222 | D0F0xBC_xE0104188_ReqSclkSel3_WIDTH, |
| 223 | (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[3]) |
| 224 | }, |
| 225 | { |
| 226 | D0F0xBC_xE0104188_VCEMclk_OFFSET + 0, |
| 227 | 1, |
| 228 | (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[0]) |
| 229 | }, |
| 230 | { |
| 231 | D0F0xBC_xE0104188_VCEMclk_OFFSET + 1, |
| 232 | 1, |
| 233 | (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[1]) |
| 234 | }, |
| 235 | { |
| 236 | D0F0xBC_xE0104188_VCEMclk_OFFSET + 2, |
| 237 | 1, |
| 238 | (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[2]) |
| 239 | }, |
| 240 | { |
| 241 | D0F0xBC_xE0104188_VCEMclk_OFFSET + 3, |
| 242 | 1, |
| 243 | (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[3]) |
| 244 | }, |
| 245 | }; |
| 246 | |
| 247 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106020_TABLE [] = { |
| 248 | { |
| 249 | D0F0xBC_xE0106020_PowerplayDClkVClkSel0_OFFSET, |
| 250 | D0F0xBC_xE0106020_PowerplayDClkVClkSel0_WIDTH, |
| 251 | (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0]) |
| 252 | }, |
| 253 | { |
| 254 | D0F0xBC_xE0106020_PowerplayDClkVClkSel1_OFFSET, |
| 255 | D0F0xBC_xE0106020_PowerplayDClkVClkSel1_WIDTH, |
| 256 | (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1]) |
| 257 | }, |
| 258 | { |
| 259 | D0F0xBC_xE0106020_PowerplayDClkVClkSel2_OFFSET, |
| 260 | D0F0xBC_xE0106020_PowerplayDClkVClkSel2_WIDTH, |
| 261 | (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2]) |
| 262 | } |
| 263 | }; |
| 264 | |
| 265 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106023_TABLE [] = { |
| 266 | { |
| 267 | D0F0xBC_xE0106023_PowerplayDClkVClkSel3_OFFSET, |
| 268 | D0F0xBC_xE0106023_PowerplayDClkVClkSel3_WIDTH, |
| 269 | (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3]) |
| 270 | } |
| 271 | }; |
| 272 | |
| 273 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106024_TABLE [] = { |
| 274 | { |
| 275 | D0F0xBC_xE0106024_PowerplayDClkVClkSel4_OFFSET, |
| 276 | D0F0xBC_xE0106024_PowerplayDClkVClkSel4_WIDTH, |
| 277 | (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4]) |
| 278 | }, |
| 279 | { |
| 280 | D0F0xBC_xE0106024_PowerplayDClkVClkSel5_OFFSET, |
| 281 | D0F0xBC_xE0106024_PowerplayDClkVClkSel5_WIDTH, |
| 282 | (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5]) |
| 283 | } |
| 284 | }; |
| 285 | |
| 286 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705C_TABLE [] = { |
| 287 | { |
| 288 | D0F0xBC_xE010705C_PowerplayTableRev_OFFSET, |
| 289 | D0F0xBC_xE010705C_PowerplayTableRev_WIDTH, |
| 290 | (UINT16) offsetof (PP_FUSE_ARRAY, PPlayTableRev) |
| 291 | }, |
| 292 | { |
| 293 | D0F0xBC_xE010705C_SClkThermDid_OFFSET, |
| 294 | D0F0xBC_xE010705C_SClkThermDid_WIDTH, |
| 295 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkThermDid) |
| 296 | }, |
| 297 | { |
| 298 | D0F0xBC_xE010705C_PcieGen2Vid_OFFSET, |
| 299 | D0F0xBC_xE010705C_PcieGen2Vid_WIDTH, |
| 300 | (UINT16) offsetof (PP_FUSE_ARRAY, PcieGen2Vid) |
| 301 | } |
| 302 | }; |
| 303 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705F_TABLE [] = { |
| 304 | { |
| 305 | D0F0xBC_xE010705F_SClkDpmVid0_OFFSET, |
| 306 | D0F0xBC_xE010705F_SClkDpmVid0_WIDTH, |
| 307 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0]) |
| 308 | }, |
| 309 | { |
| 310 | D0F0xBC_xE010705F_SClkDpmVid0_OFFSET, |
| 311 | D0F0xBC_xE010705F_SClkDpmVid0_WIDTH, |
| 312 | (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[0]) |
| 313 | } |
| 314 | }; |
| 315 | |
| 316 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107060_TABLE [] = { |
| 317 | { |
| 318 | D0F0xBC_xE0107060_SClkDpmVid1_OFFSET, |
| 319 | D0F0xBC_xE0107060_SClkDpmVid1_WIDTH, |
| 320 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1]) |
| 321 | }, |
| 322 | { |
| 323 | D0F0xBC_xE0107060_SClkDpmVid1_OFFSET, |
| 324 | D0F0xBC_xE0107060_SClkDpmVid1_WIDTH, |
| 325 | (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[1]) |
| 326 | }, |
| 327 | { |
| 328 | D0F0xBC_xE0107060_SClkDpmVid2_OFFSET, |
| 329 | D0F0xBC_xE0107060_SClkDpmVid2_WIDTH, |
| 330 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2]) |
| 331 | }, |
| 332 | { |
| 333 | D0F0xBC_xE0107060_SClkDpmVid2_OFFSET, |
| 334 | D0F0xBC_xE0107060_SClkDpmVid2_WIDTH, |
| 335 | (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[2]) |
| 336 | }, |
| 337 | { |
| 338 | D0F0xBC_xE0107060_SClkDpmVid3_OFFSET, |
| 339 | D0F0xBC_xE0107060_SClkDpmVid3_WIDTH, |
| 340 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3]) |
| 341 | }, |
| 342 | { |
| 343 | D0F0xBC_xE0107060_SClkDpmVid4_OFFSET, |
| 344 | D0F0xBC_xE0107060_SClkDpmVid4_WIDTH, |
| 345 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4]) |
| 346 | }, |
| 347 | { |
| 348 | D0F0xBC_xE0107060_SClkDpmDid0_OFFSET, |
| 349 | D0F0xBC_xE0107060_SClkDpmDid0_WIDTH, |
| 350 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0]) |
| 351 | }, |
| 352 | { |
| 353 | D0F0xBC_xE0107060_SClkDpmDid1_OFFSET, |
| 354 | D0F0xBC_xE0107060_SClkDpmDid1_WIDTH, |
| 355 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1]) |
| 356 | }, |
| 357 | { |
| 358 | D0F0xBC_xE0107060_SClkDpmDid2_OFFSET, |
| 359 | D0F0xBC_xE0107060_SClkDpmDid2_WIDTH, |
| 360 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2]) |
| 361 | } |
| 362 | }; |
| 363 | |
| 364 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107063_TABLE [] = { |
| 365 | { |
| 366 | D0F0xBC_xE0107063_SClkDpmDid3_OFFSET, |
| 367 | D0F0xBC_xE0107063_SClkDpmDid3_WIDTH, |
| 368 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3]) |
| 369 | } |
| 370 | }; |
| 371 | |
| 372 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107064_TABLE [] = { |
| 373 | { |
| 374 | D0F0xBC_xE0107064_SClkDpmDid4_OFFSET, |
| 375 | D0F0xBC_xE0107064_SClkDpmDid4_WIDTH, |
| 376 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4]) |
| 377 | } |
| 378 | }; |
| 379 | |
| 380 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107067_TABLE [] = { |
| 381 | { |
| 382 | D0F0xBC_xE0107067_DispClkDid0_OFFSET, |
| 383 | D0F0xBC_xE0107067_DispClkDid0_WIDTH, |
| 384 | (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[0]) |
| 385 | } |
| 386 | }; |
| 387 | |
| 388 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107068_TABLE [] = { |
| 389 | { |
| 390 | D0F0xBC_xE0107068_DispClkDid1_OFFSET, |
| 391 | D0F0xBC_xE0107068_DispClkDid1_WIDTH, |
| 392 | (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[1]) |
| 393 | }, |
| 394 | { |
| 395 | D0F0xBC_xE0107068_DispClkDid2_OFFSET, |
| 396 | D0F0xBC_xE0107068_DispClkDid2_WIDTH, |
| 397 | (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[2]) |
| 398 | }, |
| 399 | { |
| 400 | D0F0xBC_xE0107068_DispClkDid3_OFFSET, |
| 401 | D0F0xBC_xE0107068_DispClkDid3_WIDTH, |
| 402 | (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[3]) |
| 403 | }, |
| 404 | { |
| 405 | D0F0xBC_xE0107068_LClkDpmDid0_OFFSET, |
| 406 | D0F0xBC_xE0107068_LClkDpmDid0_WIDTH, |
| 407 | (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0]) |
| 408 | } |
| 409 | }; |
| 410 | |
| 411 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706B_TABLE [] = { |
| 412 | { |
| 413 | D0F0xBC_xE010706B_LClkDpmDid1_OFFSET, |
| 414 | D0F0xBC_xE010706B_LClkDpmDid1_WIDTH, |
| 415 | (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1]) |
| 416 | } |
| 417 | }; |
| 418 | |
| 419 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706C_TABLE [] = { |
| 420 | { |
| 421 | D0F0xBC_xE010706C_LClkDpmDid2_OFFSET, |
| 422 | D0F0xBC_xE010706C_LClkDpmDid2_WIDTH, |
| 423 | (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2]) |
| 424 | }, |
| 425 | { |
| 426 | D0F0xBC_xE010706C_LClkDpmDid3_OFFSET, |
| 427 | D0F0xBC_xE010706C_LClkDpmDid3_WIDTH, |
| 428 | (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3]) |
| 429 | }, |
| 430 | { |
| 431 | D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 0, |
| 432 | 1, |
| 433 | (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0]) |
| 434 | }, |
| 435 | { |
| 436 | D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 1, |
| 437 | 1, |
| 438 | (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1]) |
| 439 | }, |
| 440 | { |
| 441 | D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 2, |
| 442 | 1, |
| 443 | (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2]) |
| 444 | }, |
| 445 | { |
| 446 | D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 3, |
| 447 | 1, |
| 448 | (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3]) |
| 449 | }, |
| 450 | { |
| 451 | D0F0xBC_xE010706C_DClkDid0_OFFSET, |
| 452 | D0F0xBC_xE010706C_DClkDid0_WIDTH, |
| 453 | (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[0]) |
| 454 | } |
| 455 | }; |
| 456 | |
| 457 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706F_TABLE [] = { |
| 458 | { |
| 459 | D0F0xBC_xE010706F_DClkDid1_OFFSET, |
| 460 | D0F0xBC_xE010706F_DClkDid1_WIDTH, |
| 461 | (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[1]) |
| 462 | } |
| 463 | }; |
| 464 | |
| 465 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107070_TABLE [] = { |
| 466 | { |
| 467 | D0F0xBC_xE0107070_DClkDid2_OFFSET, |
| 468 | D0F0xBC_xE0107070_DClkDid2_WIDTH, |
| 469 | (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[2]) |
| 470 | }, |
| 471 | { |
| 472 | D0F0xBC_xE0107070_DClkDid3_OFFSET, |
| 473 | D0F0xBC_xE0107070_DClkDid3_WIDTH, |
| 474 | (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[3]) |
| 475 | }, |
| 476 | { |
| 477 | D0F0xBC_xE0107070_VClkDid0_OFFSET, |
| 478 | D0F0xBC_xE0107070_VClkDid0_WIDTH, |
| 479 | (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[0]) |
| 480 | } |
| 481 | }; |
| 482 | |
| 483 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107073_TABLE [] = { |
| 484 | { |
| 485 | D0F0xBC_xE0107073_VClkDid1_OFFSET, |
| 486 | D0F0xBC_xE0107073_VClkDid1_WIDTH, |
| 487 | (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[1]) |
| 488 | }, |
| 489 | }; |
| 490 | |
| 491 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107074_TABLE [] = { |
| 492 | { |
| 493 | D0F0xBC_xE0107074_VClkDid2_OFFSET, |
| 494 | D0F0xBC_xE0107074_VClkDid2_WIDTH, |
| 495 | (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[2]) |
| 496 | }, |
| 497 | { |
| 498 | D0F0xBC_xE0107074_VClkDid3_OFFSET, |
| 499 | D0F0xBC_xE0107074_VClkDid3_WIDTH, |
| 500 | (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[3]) |
| 501 | }, |
| 502 | { |
| 503 | D0F0xBC_xE0107074_PowerplaySclkDpmValid0_OFFSET, |
| 504 | D0F0xBC_xE0107074_PowerplaySclkDpmValid0_WIDTH, |
| 505 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0]) |
| 506 | }, |
| 507 | { |
| 508 | D0F0xBC_xE0107074_PowerplaySclkDpmValid1_OFFSET, |
| 509 | D0F0xBC_xE0107074_PowerplaySclkDpmValid1_WIDTH, |
| 510 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1]) |
| 511 | }, |
| 512 | { |
| 513 | D0F0xBC_xE0107074_PowerplaySclkDpmValid2_OFFSET, |
| 514 | D0F0xBC_xE0107074_PowerplaySclkDpmValid2_WIDTH, |
| 515 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2]) |
| 516 | } |
| 517 | }; |
| 518 | |
| 519 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107077_TABLE [] = { |
| 520 | { |
| 521 | D0F0xBC_xE0107077_PowerplaySclkDpmValid3_OFFSET, |
| 522 | D0F0xBC_xE0107077_PowerplaySclkDpmValid3_WIDTH, |
| 523 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3]) |
| 524 | } |
| 525 | }; |
| 526 | |
| 527 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107078_TABLE [] = { |
| 528 | { |
| 529 | D0F0xBC_xE0107078_PowerplaySclkDpmValid4_OFFSET, |
| 530 | D0F0xBC_xE0107078_PowerplaySclkDpmValid4_WIDTH, |
| 531 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4]) |
| 532 | }, |
| 533 | { |
| 534 | D0F0xBC_xE0107078_PowerplaySclkDpmValid5_OFFSET, |
| 535 | D0F0xBC_xE0107078_PowerplaySclkDpmValid5_WIDTH, |
| 536 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5]) |
| 537 | }, |
| 538 | { |
| 539 | D0F0xBC_xE0107078_PowerplayPolicyLabel0_OFFSET, |
| 540 | D0F0xBC_xE0107078_PowerplayPolicyLabel0_WIDTH, |
| 541 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[0]) |
| 542 | }, |
| 543 | { |
| 544 | D0F0xBC_xE0107078_PowerplayPolicyLabel1_OFFSET, |
| 545 | D0F0xBC_xE0107078_PowerplayPolicyLabel1_WIDTH, |
| 546 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[1]) |
| 547 | }, |
| 548 | { |
| 549 | D0F0xBC_xE0107078_PowerplayPolicyLabel2_OFFSET, |
| 550 | D0F0xBC_xE0107078_PowerplayPolicyLabel2_WIDTH, |
| 551 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[2]) |
| 552 | }, |
| 553 | { |
| 554 | D0F0xBC_xE0107078_PowerplayPolicyLabel3_OFFSET, |
| 555 | D0F0xBC_xE0107078_PowerplayPolicyLabel3_WIDTH, |
| 556 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[3]) |
| 557 | }, |
| 558 | { |
| 559 | D0F0xBC_xE0107078_PowerplayPolicyLabel4_OFFSET, |
| 560 | D0F0xBC_xE0107078_PowerplayPolicyLabel4_WIDTH, |
| 561 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[4]) |
| 562 | }, |
| 563 | { |
| 564 | D0F0xBC_xE0107078_PowerplayPolicyLabel5_OFFSET, |
| 565 | D0F0xBC_xE0107078_PowerplayPolicyLabel5_WIDTH, |
| 566 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[5]) |
| 567 | } |
| 568 | }; |
| 569 | |
| 570 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707B_TABLE [] = { |
| 571 | { |
| 572 | D0F0xBC_xE010707B_PowerplayStateFlag0_OFFSET, |
| 573 | D0F0xBC_xE010707B_PowerplayStateFlag0_WIDTH, |
| 574 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[0]) |
| 575 | } |
| 576 | }; |
| 577 | |
| 578 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707C_TABLE [] = { |
| 579 | { |
| 580 | D0F0xBC_xE010707C_PowerplayStateFlag1_OFFSET, |
| 581 | D0F0xBC_xE010707C_PowerplayStateFlag1_WIDTH, |
| 582 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[1]) |
| 583 | }, |
| 584 | { |
| 585 | D0F0xBC_xE010707C_PowerplayStateFlag2_OFFSET, |
| 586 | D0F0xBC_xE010707C_PowerplayStateFlag2_WIDTH, |
| 587 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[2]) |
| 588 | }, |
| 589 | { |
| 590 | D0F0xBC_xE010707C_PowerplayStateFlag3_OFFSET, |
| 591 | D0F0xBC_xE010707C_PowerplayStateFlag3_WIDTH, |
| 592 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[3]) |
| 593 | }, |
| 594 | { |
| 595 | D0F0xBC_xE010707C_PowerplayStateFlag4_OFFSET, |
| 596 | D0F0xBC_xE010707C_PowerplayStateFlag4_WIDTH, |
| 597 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[4]) |
| 598 | } |
| 599 | }; |
| 600 | |
| 601 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707F_TABLE [] = { |
| 602 | { |
| 603 | D0F0xBC_xE010707F_PowerplayStateFlag5_OFFSET, |
| 604 | D0F0xBC_xE010707F_PowerplayStateFlag5_WIDTH, |
| 605 | (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[5]) |
| 606 | } |
| 607 | }; |
| 608 | |
| 609 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xFF000000_TABLE [] = { |
| 610 | { |
| 611 | D0F0xBC_xFF000000_MainPllOpFreqIdStartup_OFFSET, |
| 612 | D0F0xBC_xFF000000_MainPllOpFreqIdStartup_WIDTH, |
| 613 | (UINT16) offsetof (PP_FUSE_ARRAY, MainPllId) |
| 614 | } |
| 615 | }; |
| 616 | |
| 617 | FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0001008_TABLE [] = { |
| 618 | { |
| 619 | D0F0xBC_xE0001008_SClkVid0_OFFSET, |
| 620 | D0F0xBC_xE0001008_SClkVid0_WIDTH, |
| 621 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[0]) |
| 622 | }, |
| 623 | { |
| 624 | D0F0xBC_xE0001008_SClkVid1_OFFSET, |
| 625 | D0F0xBC_xE0001008_SClkVid1_WIDTH, |
| 626 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[1]) |
| 627 | }, |
| 628 | { |
| 629 | D0F0xBC_xE0001008_SClkVid2_OFFSET, |
| 630 | D0F0xBC_xE0001008_SClkVid2_WIDTH, |
| 631 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[2]) |
| 632 | }, |
| 633 | { |
| 634 | D0F0xBC_xE0001008_SClkVid3_OFFSET, |
| 635 | D0F0xBC_xE0001008_SClkVid3_WIDTH, |
| 636 | (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[3]) |
| 637 | } |
| 638 | }; |
| 639 | |
| 640 | |
| 641 | FUSE_TABLE_ENTRY_TN FuseRegisterTableTN [] = { |
| 642 | { |
| 643 | D0F0xBC_xE0104158_TYPE, |
| 644 | D0F0xBC_xE0104158_ADDRESS, |
| 645 | sizeof (D0F0xBC_xE0104158_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 646 | D0F0xBC_xE0104158_TABLE |
| 647 | }, |
| 648 | { |
| 649 | D0F0xBC_xE010415B_TYPE, |
| 650 | D0F0xBC_xE010415B_ADDRESS, |
| 651 | sizeof (D0F0xBC_xE010415B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 652 | D0F0xBC_xE010415B_TABLE |
| 653 | }, |
| 654 | { |
| 655 | D0F0xBC_xE0104184_TYPE, |
| 656 | D0F0xBC_xE0104184_ADDRESS, |
| 657 | sizeof (D0F0xBC_xE0104184_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 658 | D0F0xBC_xE0104184_TABLE |
| 659 | }, |
| 660 | { |
| 661 | D0F0xBC_xE0104187_TYPE, |
| 662 | D0F0xBC_xE0104187_ADDRESS, |
| 663 | sizeof (D0F0xBC_xE0104187_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 664 | D0F0xBC_xE0104187_TABLE |
| 665 | }, |
| 666 | { |
| 667 | D0F0xBC_xE0104188_TYPE, |
| 668 | D0F0xBC_xE0104188_ADDRESS, |
| 669 | sizeof (D0F0xBC_xE0104188_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 670 | D0F0xBC_xE0104188_TABLE |
| 671 | }, |
| 672 | { |
| 673 | D0F0xBC_xE0106020_TYPE, |
| 674 | D0F0xBC_xE0106020_ADDRESS, |
| 675 | sizeof (D0F0xBC_xE0106020_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 676 | D0F0xBC_xE0106020_TABLE |
| 677 | }, |
| 678 | { |
| 679 | D0F0xBC_xE0106023_TYPE, |
| 680 | D0F0xBC_xE0106023_ADDRESS, |
| 681 | sizeof (D0F0xBC_xE0106023_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 682 | D0F0xBC_xE0106023_TABLE |
| 683 | }, |
| 684 | { |
| 685 | D0F0xBC_xE0106024_TYPE, |
| 686 | D0F0xBC_xE0106024_ADDRESS, |
| 687 | sizeof (D0F0xBC_xE0106024_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 688 | D0F0xBC_xE0106024_TABLE |
| 689 | }, |
| 690 | { |
| 691 | D0F0xBC_xE010705C_TYPE, |
| 692 | D0F0xBC_xE010705C_ADDRESS, |
| 693 | sizeof (D0F0xBC_xE010705C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 694 | D0F0xBC_xE010705C_TABLE |
| 695 | }, |
| 696 | { |
| 697 | D0F0xBC_xE010705F_TYPE, |
| 698 | D0F0xBC_xE010705F_ADDRESS, |
| 699 | sizeof (D0F0xBC_xE010705F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 700 | D0F0xBC_xE010705F_TABLE |
| 701 | }, |
| 702 | { |
| 703 | D0F0xBC_xE0107060_TYPE, |
| 704 | D0F0xBC_xE0107060_ADDRESS, |
| 705 | sizeof (D0F0xBC_xE0107060_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 706 | D0F0xBC_xE0107060_TABLE |
| 707 | }, |
| 708 | { |
| 709 | D0F0xBC_xE0107063_TYPE, |
| 710 | D0F0xBC_xE0107063_ADDRESS, |
| 711 | sizeof (D0F0xBC_xE0107063_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 712 | D0F0xBC_xE0107063_TABLE |
| 713 | }, |
| 714 | { |
| 715 | D0F0xBC_xE0107064_TYPE, |
| 716 | D0F0xBC_xE0107064_ADDRESS, |
| 717 | sizeof (D0F0xBC_xE0107064_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 718 | D0F0xBC_xE0107064_TABLE |
| 719 | }, |
| 720 | { |
| 721 | D0F0xBC_xE0107067_TYPE, |
| 722 | D0F0xBC_xE0107067_ADDRESS, |
| 723 | sizeof (D0F0xBC_xE0107067_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 724 | D0F0xBC_xE0107067_TABLE |
| 725 | }, |
| 726 | { |
| 727 | D0F0xBC_xE0107068_TYPE, |
| 728 | D0F0xBC_xE0107068_ADDRESS, |
| 729 | sizeof (D0F0xBC_xE0107068_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 730 | D0F0xBC_xE0107068_TABLE |
| 731 | }, |
| 732 | { |
| 733 | D0F0xBC_xE010706B_TYPE, |
| 734 | D0F0xBC_xE010706B_ADDRESS, |
| 735 | sizeof (D0F0xBC_xE010706B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 736 | D0F0xBC_xE010706B_TABLE |
| 737 | }, |
| 738 | { |
| 739 | D0F0xBC_xE010706C_TYPE, |
| 740 | D0F0xBC_xE010706C_ADDRESS, |
| 741 | sizeof (D0F0xBC_xE010706C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 742 | D0F0xBC_xE010706C_TABLE |
| 743 | }, |
| 744 | { |
| 745 | D0F0xBC_xE010706F_TYPE, |
| 746 | D0F0xBC_xE010706F_ADDRESS, |
| 747 | sizeof (D0F0xBC_xE010706F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 748 | D0F0xBC_xE010706F_TABLE |
| 749 | }, |
| 750 | { |
| 751 | D0F0xBC_xE0107070_TYPE, |
| 752 | D0F0xBC_xE0107070_ADDRESS, |
| 753 | sizeof (D0F0xBC_xE0107070_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 754 | D0F0xBC_xE0107070_TABLE |
| 755 | }, |
| 756 | { |
| 757 | D0F0xBC_xE0107073_TYPE, |
| 758 | D0F0xBC_xE0107073_ADDRESS, |
| 759 | sizeof (D0F0xBC_xE0107073_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 760 | D0F0xBC_xE0107073_TABLE |
| 761 | }, |
| 762 | { |
| 763 | D0F0xBC_xE0107074_TYPE, |
| 764 | D0F0xBC_xE0107074_ADDRESS, |
| 765 | sizeof (D0F0xBC_xE0107074_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 766 | D0F0xBC_xE0107074_TABLE |
| 767 | }, |
| 768 | { |
| 769 | D0F0xBC_xE0107077_TYPE, |
| 770 | D0F0xBC_xE0107077_ADDRESS, |
| 771 | sizeof (D0F0xBC_xE0107077_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 772 | D0F0xBC_xE0107077_TABLE |
| 773 | }, |
| 774 | { |
| 775 | D0F0xBC_xE0107078_TYPE, |
| 776 | D0F0xBC_xE0107078_ADDRESS, |
| 777 | sizeof (D0F0xBC_xE0107078_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 778 | D0F0xBC_xE0107078_TABLE |
| 779 | }, |
| 780 | { |
| 781 | D0F0xBC_xE010707B_TYPE, |
| 782 | D0F0xBC_xE010707B_ADDRESS, |
| 783 | sizeof (D0F0xBC_xE010707B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 784 | D0F0xBC_xE010707B_TABLE |
| 785 | }, |
| 786 | { |
| 787 | D0F0xBC_xE010707C_TYPE, |
| 788 | D0F0xBC_xE010707C_ADDRESS, |
| 789 | sizeof (D0F0xBC_xE010707C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 790 | D0F0xBC_xE010707C_TABLE |
| 791 | }, |
| 792 | { |
| 793 | D0F0xBC_xE010707F_TYPE, |
| 794 | D0F0xBC_xE010707F_ADDRESS, |
| 795 | sizeof (D0F0xBC_xE010707F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 796 | D0F0xBC_xE010707F_TABLE |
| 797 | }, |
| 798 | { |
| 799 | D0F0xBC_xFF000000_TYPE, |
| 800 | D0F0xBC_xFF000000_ADDRESS, |
| 801 | sizeof (D0F0xBC_xFF000000_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 802 | D0F0xBC_xFF000000_TABLE |
| 803 | }, |
| 804 | { |
| 805 | D0F0xBC_xE0001008_TYPE, |
| 806 | D0F0xBC_xE0001008_ADDRESS, |
| 807 | sizeof (D0F0xBC_xE0001008_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), |
| 808 | D0F0xBC_xE0001008_TABLE |
| 809 | } |
| 810 | }; |
| 811 | |
| 812 | FUSE_TABLE_TN FuseTableTN = { |
| 813 | sizeof (FuseRegisterTableTN) / sizeof (FUSE_TABLE_ENTRY_TN), |
| 814 | FuseRegisterTableTN |
| 815 | }; |
| 816 | |
| 817 | /*----------------------------------------------------------------------------------------*/ |
| 818 | /** |
| 819 | * Load Fuse Table TN |
| 820 | * |
| 821 | * |
| 822 | * @param[out] PpFuseArray Pointer to save fuse table |
| 823 | * @param[in] StdHeader Pointer to Standard configuration |
| 824 | * @retval AGESA_STATUS |
| 825 | */ |
| 826 | |
| 827 | STATIC VOID |
| 828 | NbFuseLoadFuseTableTN ( |
| 829 | OUT PP_FUSE_ARRAY *PpFuseArray, |
| 830 | IN AMD_CONFIG_PARAMS *StdHeader |
| 831 | ) |
| 832 | { |
| 833 | FUSE_TABLE_TN *FuseTable; |
| 834 | UINTN RegisterIndex; |
| 835 | FuseTable = &FuseTableTN; |
| 836 | for (RegisterIndex = 0; RegisterIndex < FuseTable->FuseTableLength; RegisterIndex++ ) { |
| 837 | UINTN FieldIndex; |
| 838 | UINTN FuseRegisterTableLength; |
| 839 | UINT32 FuseValue; |
| 840 | FuseRegisterTableLength = FuseTable->FuseTable[RegisterIndex].FuseRegisterTableLength; |
| 841 | |
| 842 | GnbRegisterReadTN ( |
| 843 | FuseTable->FuseTable[RegisterIndex].RegisterSpaceType, |
| 844 | FuseTable->FuseTable[RegisterIndex].Register, |
| 845 | &FuseValue, |
| 846 | 0, |
| 847 | StdHeader |
| 848 | ); |
| 849 | for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength; FieldIndex++) { |
| 850 | FUSE_REGISTER_ENTRY_TN RegisterEntry; |
| 851 | RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex]; |
| 852 | *((UINT8 *) PpFuseArray + RegisterEntry.FuseOffset) = (UINT8) ((FuseValue >> RegisterEntry.FieldOffset) & |
| 853 | ((1 << RegisterEntry.FieldWidth) - 1)); |
| 854 | } |
| 855 | } |
| 856 | } |
| 857 | |
| 858 | /*----------------------------------------------------------------------------------------*/ |
| 859 | /** |
| 860 | * Gnb load fuse table |
| 861 | * |
| 862 | * |
| 863 | * |
| 864 | * @param[in] StdHeader Pointer to Standard configuration |
| 865 | * @retval AGESA_STATUS |
| 866 | */ |
| 867 | |
| 868 | AGESA_STATUS |
| 869 | GnbLoadFuseTableTN ( |
| 870 | IN AMD_CONFIG_PARAMS *StdHeader |
| 871 | ) |
| 872 | { |
| 873 | PP_FUSE_ARRAY *PpFuseArray; |
| 874 | AGESA_STATUS Status; |
| 875 | D18F3xA0_STRUCT D18F3xA0; |
| 876 | |
| 877 | Status = AGESA_SUCCESS; |
| 878 | IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Enter\n"); |
| 879 | |
| 880 | PpFuseArray = (PP_FUSE_ARRAY *) GnbAllocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, sizeof (PP_FUSE_ARRAY), StdHeader); |
| 881 | ASSERT (PpFuseArray != NULL); |
| 882 | if (PpFuseArray != NULL) { |
| 883 | //Support for real fuste table |
| 884 | GnbRegisterReadTN (D18F3xA0_TYPE, D18F3xA0_ADDRESS, &D18F3xA0.Value, 0, StdHeader); |
| 885 | if ((D18F3xA0.Field.CofVidProg) && (GnbBuildOptions.GnbLoadRealFuseTable)) { |
| 886 | NbFuseLoadFuseTableTN (PpFuseArray, StdHeader); |
| 887 | PpFuseArray->VceSateTableSupport = TRUE; |
| 888 | IDS_HDT_CONSOLE (NB_MISC, " Processor Fused\n"); |
| 889 | } else { |
| 890 | LibAmdMemCopy (PpFuseArray, &ex907 , sizeof (PP_FUSE_ARRAY), StdHeader); |
| 891 | IDS_HDT_CONSOLE (NB_MISC, " Processor Unfuse\n"); |
| 892 | } |
| 893 | } else { |
| 894 | Status = AGESA_ERROR; |
| 895 | } |
| 896 | IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPFUSE_OVERRIDE, PpFuseArray, StdHeader); |
| 897 | GnbFuseTableDebugDumpTN (PpFuseArray, StdHeader); |
| 898 | IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Exit [0x%x]\n", Status); |
| 899 | return Status; |
| 900 | } |
| 901 | |
| 902 | |
| 903 | /*----------------------------------------------------------------------------------------*/ |
| 904 | /** |
| 905 | * Debug dump fuse table |
| 906 | * |
| 907 | * |
| 908 | * @param[out] PpFuseArray Pointer to save fuse table |
| 909 | * @param[in] StdHeader Pointer to Standard configuration |
| 910 | */ |
| 911 | |
| 912 | VOID |
| 913 | GnbFuseTableDebugDumpTN ( |
| 914 | IN PP_FUSE_ARRAY *PpFuseArray, |
| 915 | IN AMD_CONFIG_PARAMS *StdHeader |
| 916 | ) |
| 917 | { |
| 918 | UINTN Index; |
| 919 | |
| 920 | IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n"); |
| 921 | for (Index = 0; Index < 4; Index++) { |
| 922 | if (PpFuseArray->LclkDpmValid[Index] != 0) { |
| 923 | IDS_HDT_CONSOLE ( |
| 924 | NB_MISC, |
| 925 | " LCLK DID[%d] - 0x%02x (%dMHz)\n", |
| 926 | Index, |
| 927 | PpFuseArray->LclkDpmDid[Index], |
| 928 | (PpFuseArray->LclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->LclkDpmDid[Index], StdHeader) / 100) : 0 |
| 929 | ); |
| 930 | IDS_HDT_CONSOLE (NB_MISC, " LCLK VID[%d] - 0x02%x\n", Index, PpFuseArray->LclkDpmVid[Index]); |
| 931 | } |
| 932 | } |
| 933 | for (Index = 0; Index < 4; Index++) { |
| 934 | IDS_HDT_CONSOLE ( |
| 935 | NB_MISC, |
| 936 | " VCLK DID[%d] - 0x%02x (%dMHz)\n", |
| 937 | Index, |
| 938 | PpFuseArray->VclkDid[Index], |
| 939 | (PpFuseArray->VclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->VclkDid[Index], StdHeader) / 100) : 0 |
| 940 | ); |
| 941 | IDS_HDT_CONSOLE ( |
| 942 | NB_MISC, |
| 943 | " DCLK DID[%d] - 0x%02x (%dMHz)\n", |
| 944 | Index, |
| 945 | PpFuseArray->DclkDid[Index], |
| 946 | (PpFuseArray->DclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DclkDid[Index], StdHeader) / 100) : 0 |
| 947 | ); |
| 948 | } |
| 949 | for (Index = 0; Index < 4; Index++) { |
| 950 | IDS_HDT_CONSOLE ( |
| 951 | NB_MISC, |
| 952 | " DISPCLK DID[%d] - 0x%02x (%dMHz)\n", |
| 953 | Index, |
| 954 | PpFuseArray->DisplclkDid[Index], |
| 955 | (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DisplclkDid[Index], StdHeader) / 100) : 0 |
| 956 | ); |
| 957 | } |
| 958 | for (Index = 0; Index < 4; Index++) { |
| 959 | IDS_HDT_CONSOLE ( |
| 960 | NB_MISC, |
| 961 | " ECLK DID[%d] - 0x%02x (%dMHz)\n", |
| 962 | Index, |
| 963 | PpFuseArray->EclkDid[Index], |
| 964 | (PpFuseArray->EclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->EclkDid[Index], StdHeader) / 100) : 0 |
| 965 | ); |
| 966 | IDS_HDT_CONSOLE ( |
| 967 | NB_MISC, |
| 968 | " VCE SCLK DID[%d] - 0x%02x (%dMHz)\n", |
| 969 | Index, |
| 970 | PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]], |
| 971 | (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]], StdHeader) / 100) : 0 |
| 972 | ); |
| 973 | IDS_HDT_CONSOLE ( |
| 974 | NB_MISC, |
| 975 | " VCE Flags[ % d] - 0x % 02x\n", |
| 976 | Index, |
| 977 | PpFuseArray->VceFlags[Index] |
| 978 | ); |
| 979 | } |
| 980 | for (Index = 0; Index < 6; Index++) { |
| 981 | IDS_HDT_CONSOLE ( |
| 982 | NB_MISC, |
| 983 | " SCLK DID[%d] - 0x%02x (%dMHz)\n", |
| 984 | Index, |
| 985 | PpFuseArray->SclkDpmDid[Index], |
| 986 | (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[Index], StdHeader) / 100) : 0 |
| 987 | ); |
| 988 | IDS_HDT_CONSOLE ( |
| 989 | NB_MISC, |
| 990 | " SCLK TDP[%d] - 0x%x \n", |
| 991 | Index, |
| 992 | PpFuseArray->SclkDpmTdpLimit[Index] |
| 993 | ); |
| 994 | IDS_HDT_CONSOLE (NB_MISC, " SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]); |
| 995 | } |
| 996 | for (Index = 0; Index < 6; Index++) { |
| 997 | IDS_HDT_CONSOLE (NB_MISC, " State #%d\n", Index); |
| 998 | } |
| 999 | IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n"); |
| 1000 | } |