zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame^] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * PCIe late post initialization. |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 64152 $ @e \$Date: 2012-01-16 21:38:07 -0600 (Mon, 16 Jan 2012) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. |
| 19 | * |
| 20 | * AMD is granting you permission to use this software (the Materials) |
| 21 | * pursuant to the terms and conditions of your Software License Agreement |
| 22 | * with AMD. This header does *NOT* give you permission to use the Materials |
| 23 | * or any rights under AMD's intellectual property. Your use of any portion |
| 24 | * of these Materials shall constitute your acceptance of those terms and |
| 25 | * conditions. If you do not agree to the terms and conditions of the Software |
| 26 | * License Agreement, please do not use any portion of these Materials. |
| 27 | * |
| 28 | * CONFIDENTIALITY: The Materials and all other information, identified as |
| 29 | * confidential and provided to you by AMD shall be kept confidential in |
| 30 | * accordance with the terms and conditions of the Software License Agreement. |
| 31 | * |
| 32 | * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION |
| 33 | * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED |
| 34 | * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF |
| 35 | * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, |
| 36 | * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. |
| 37 | * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER |
| 38 | * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS |
| 39 | * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, |
| 40 | * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER |
| 41 | * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF |
| 42 | * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE |
| 43 | * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, |
| 44 | * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. |
| 45 | * |
| 46 | * AMD does not assume any responsibility for any errors which may appear in |
| 47 | * the Materials or any other related information provided to you by AMD, or |
| 48 | * result from use of the Materials or any related information. |
| 49 | * |
| 50 | * You agree that you will not reverse engineer or decompile the Materials. |
| 51 | * |
| 52 | * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any |
| 53 | * further information, software, technical information, know-how, or show-how |
| 54 | * available to you. Additionally, AMD retains the right to modify the |
| 55 | * Materials at any time, without notice, and is not obligated to provide such |
| 56 | * modified Materials to you. |
| 57 | * |
| 58 | * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with |
| 59 | * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is |
| 60 | * subject to the restrictions as set forth in FAR 52.227-14 and |
| 61 | * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the |
| 62 | * Government constitutes acknowledgement of AMD's proprietary rights in them. |
| 63 | * |
| 64 | * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any |
| 65 | * direct product thereof will be exported directly or indirectly, into any |
| 66 | * country prohibited by the United States Export Administration Act and the |
| 67 | * regulations thereunder, without the required authorization from the U.S. |
| 68 | * government nor will be used for any purpose prohibited by the same. |
| 69 | * *************************************************************************** |
| 70 | * |
| 71 | */ |
| 72 | /*---------------------------------------------------------------------------------------- |
| 73 | * M O D U L E S U S E D |
| 74 | *---------------------------------------------------------------------------------------- |
| 75 | */ |
| 76 | #include "AGESA.h" |
| 77 | #include "Ids.h" |
| 78 | #include "Gnb.h" |
| 79 | #include "GnbGfx.h" |
| 80 | #include "GnbCommonLib.h" |
| 81 | #include "GnbTable.h" |
| 82 | #include "GnbPcieConfig.h" |
| 83 | #include "GnbRegisterAccTN.h" |
| 84 | #include "cpuFamilyTranslation.h" |
| 85 | #include "GnbRegistersTN.h" |
| 86 | #include "GfxLibTN.h" |
| 87 | #include "GfxGmcInitTN.h" |
| 88 | #include "Filecode.h" |
| 89 | #define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE |
| 90 | /*---------------------------------------------------------------------------------------- |
| 91 | * D E F I N I T I O N S A N D M A C R O S |
| 92 | *---------------------------------------------------------------------------------------- |
| 93 | */ |
| 94 | |
| 95 | extern GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN []; |
| 96 | extern GNB_TABLE ROMDATA GfxGmcInitTableTN []; |
| 97 | extern GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN []; |
| 98 | |
| 99 | |
| 100 | #define GNB_GFX_DRAM_CH_0_PRESENT 1 |
| 101 | #define GNB_GFX_DRAM_CH_1_PRESENT 2 |
| 102 | |
| 103 | /*---------------------------------------------------------------------------------------- |
| 104 | * T Y P E D E F S A N D S T R U C T U R E S |
| 105 | *---------------------------------------------------------------------------------------- |
| 106 | */ |
| 107 | |
| 108 | DCT_REGISTER_ENTRY DctRegisterTable [] = { |
| 109 | { |
| 110 | TYPE_D18F2_dct0, |
| 111 | D18F2x94_dct0_ADDRESS, |
| 112 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct0) |
| 113 | }, |
| 114 | { |
| 115 | TYPE_D18F2_dct1, |
| 116 | D18F2x94_dct1_ADDRESS, |
| 117 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct1) |
| 118 | }, |
| 119 | { |
| 120 | TYPE_D18F2_dct0, |
| 121 | D18F2x2E0_dct0_ADDRESS, |
| 122 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct0) |
| 123 | }, |
| 124 | { |
| 125 | TYPE_D18F2_dct1, |
| 126 | D18F2x2E0_dct1_ADDRESS, |
| 127 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct1) |
| 128 | }, |
| 129 | { |
| 130 | TYPE_D18F2_dct0_mp0, |
| 131 | D18F2x200_dct0_mp0_ADDRESS, |
| 132 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp0) |
| 133 | }, |
| 134 | { |
| 135 | TYPE_D18F2_dct0_mp1, |
| 136 | D18F2x200_dct0_mp1_ADDRESS, |
| 137 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp1) |
| 138 | }, |
| 139 | { |
| 140 | TYPE_D18F2_dct1_mp0, |
| 141 | D18F2x200_dct1_mp0_ADDRESS, |
| 142 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp0) |
| 143 | }, |
| 144 | { |
| 145 | TYPE_D18F2_dct1_mp1, |
| 146 | D18F2x200_dct1_mp1_ADDRESS, |
| 147 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp1) |
| 148 | }, |
| 149 | { |
| 150 | TYPE_D18F2_dct0_mp0, |
| 151 | D18F2x204_dct0_mp0_ADDRESS, |
| 152 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp0) |
| 153 | }, |
| 154 | { |
| 155 | TYPE_D18F2_dct0_mp1, |
| 156 | D18F2x204_dct0_mp1_ADDRESS, |
| 157 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp1) |
| 158 | }, |
| 159 | { |
| 160 | TYPE_D18F2_dct1_mp0, |
| 161 | D18F2x204_dct1_mp0_ADDRESS, |
| 162 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp0) |
| 163 | }, |
| 164 | { |
| 165 | TYPE_D18F2_dct1_mp1, |
| 166 | D18F2x204_dct1_mp1_ADDRESS, |
| 167 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp1) |
| 168 | }, |
| 169 | { |
| 170 | TYPE_D18F2_dct0_mp0, |
| 171 | D18F2x22C_dct0_mp0_ADDRESS, |
| 172 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp0) |
| 173 | }, |
| 174 | { |
| 175 | TYPE_D18F2_dct0_mp1, |
| 176 | D18F2x22C_dct0_mp1_ADDRESS, |
| 177 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp1) |
| 178 | }, |
| 179 | { |
| 180 | TYPE_D18F2_dct1_mp0, |
| 181 | D18F2x22C_dct1_mp0_ADDRESS, |
| 182 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp0) |
| 183 | }, |
| 184 | { |
| 185 | TYPE_D18F2_dct1_mp1, |
| 186 | D18F2x22C_dct1_mp1_ADDRESS, |
| 187 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp1) |
| 188 | }, |
| 189 | { |
| 190 | TYPE_D18F2_dct0_mp0, |
| 191 | D18F2x21C_dct0_mp0_ADDRESS, |
| 192 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp0) |
| 193 | }, |
| 194 | { |
| 195 | TYPE_D18F2_dct0_mp1, |
| 196 | D18F2x21C_dct0_mp1_ADDRESS, |
| 197 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp1) |
| 198 | }, |
| 199 | { |
| 200 | TYPE_D18F2_dct1_mp0, |
| 201 | D18F2x21C_dct1_mp0_ADDRESS, |
| 202 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp0) |
| 203 | }, |
| 204 | { |
| 205 | TYPE_D18F2_dct1_mp1, |
| 206 | D18F2x21C_dct1_mp1_ADDRESS, |
| 207 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp1) |
| 208 | }, |
| 209 | { |
| 210 | TYPE_D18F2_dct0_mp0, |
| 211 | D18F2x20C_dct0_mp0_ADDRESS, |
| 212 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp0) |
| 213 | }, |
| 214 | { |
| 215 | TYPE_D18F2_dct0_mp1, |
| 216 | D18F2x20C_dct0_mp1_ADDRESS, |
| 217 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp1) |
| 218 | }, |
| 219 | { |
| 220 | TYPE_D18F2_dct1_mp0, |
| 221 | D18F2x20C_dct1_mp0_ADDRESS, |
| 222 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp0) |
| 223 | }, |
| 224 | { |
| 225 | TYPE_D18F2_dct1_mp1, |
| 226 | D18F2x20C_dct1_mp1_ADDRESS, |
| 227 | (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp1) |
| 228 | } |
| 229 | }; |
| 230 | |
| 231 | /*---------------------------------------------------------------------------------------- |
| 232 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 233 | *---------------------------------------------------------------------------------------- |
| 234 | */ |
| 235 | |
| 236 | /*----------------------------------------------------------------------------------------*/ |
| 237 | /** |
| 238 | * Initialize Fb location |
| 239 | * |
| 240 | * |
| 241 | * |
| 242 | * @param[in] Gfx Pointer to global GFX configuration |
| 243 | * |
| 244 | */ |
| 245 | STATIC VOID |
| 246 | GfxGmcInitializeFbLocationTN ( |
| 247 | IN GFX_PLATFORM_CONFIG *Gfx |
| 248 | ) |
| 249 | { |
| 250 | GMMx2024_STRUCT GMMx2024; |
| 251 | GMMx2068_STRUCT GMMx2068; |
| 252 | GMMx2C04_STRUCT GMMx2C04; |
| 253 | GMMx5428_STRUCT GMMx5428; |
| 254 | UINT64 FBBase; |
| 255 | UINT64 FBTop; |
| 256 | FBBase = 0x0F00000000; |
| 257 | FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1; |
| 258 | GMMx2024.Value = 0; |
| 259 | GMMx2C04.Value = 0; |
| 260 | GMMx2024.Field.FB_BASE = (UINT16) (FBBase >> 24); |
| 261 | GMMx2024.Field.FB_TOP = (UINT16) (FBTop >> 24); |
| 262 | GMMx2068.Field.FB_OFFSET = (UINT32) (Gfx->UmaInfo.UmaBase >> 22); |
| 263 | GMMx2C04.Field.NONSURF_BASE = (UINT32) (FBBase >> 8); |
| 264 | GMMx5428.Field.CONFIG_MEMSIZE = Gfx->UmaInfo.UmaSize >> 20; |
| 265 | GnbRegisterWriteTN (GMMx2024_TYPE, GMMx2024_ADDRESS, &GMMx2024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 266 | GnbRegisterWriteTN (GMMx2068_TYPE, GMMx2068_ADDRESS, &GMMx2068.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 267 | GnbRegisterWriteTN (GMMx2C04_TYPE, GMMx2C04_ADDRESS, &GMMx2C04.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 268 | GnbRegisterWriteTN (GMMx5428_TYPE, GMMx5428_ADDRESS, &GMMx5428.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 269 | } |
| 270 | |
| 271 | /*----------------------------------------------------------------------------------------*/ |
| 272 | /** |
| 273 | * Get Sequencer model info |
| 274 | * |
| 275 | * |
| 276 | * @param[out] DctChannelInfo Various DCT/GMM info |
| 277 | * @param[in] Gfx Pointer to global GFX configuration |
| 278 | */ |
| 279 | |
| 280 | STATIC VOID |
| 281 | GfxGmcDctMemoryChannelInfoTN ( |
| 282 | OUT DCT_CHANNEL_INFO *DctChannelInfo, |
| 283 | IN GFX_PLATFORM_CONFIG *Gfx |
| 284 | ) |
| 285 | { |
| 286 | |
| 287 | UINT32 Index; |
| 288 | UINT32 Value; |
| 289 | |
| 290 | for (Index = 0; Index < (sizeof (DctRegisterTable) / sizeof (DCT_REGISTER_ENTRY)); Index++) { |
| 291 | GnbRegisterReadTN ( |
| 292 | DctRegisterTable[Index].RegisterSpaceType, |
| 293 | DctRegisterTable[Index].Address, |
| 294 | &Value, |
| 295 | 0, |
| 296 | GnbLibGetHeader (Gfx) |
| 297 | ); |
| 298 | *(UINT32 *)((UINT8 *) DctChannelInfo + DctRegisterTable[Index].DctChannelInfoTableOffset) = Value; |
| 299 | } |
| 300 | } |
| 301 | |
| 302 | /*----------------------------------------------------------------------------------------*/ |
| 303 | /** |
| 304 | * Initialize sequencer model |
| 305 | * |
| 306 | * |
| 307 | * |
| 308 | * @param[in] Gfx Pointer to global GFX configuration |
| 309 | * |
| 310 | */ |
| 311 | STATIC VOID |
| 312 | GfxGmcInitializeSequencerTN ( |
| 313 | IN GFX_PLATFORM_CONFIG *Gfx |
| 314 | ) |
| 315 | { |
| 316 | |
| 317 | UINT32 memps0_freq; |
| 318 | UINT32 memps1_freq; |
| 319 | UINT32 scale_mp0; |
| 320 | UINT32 scale_mp1; |
| 321 | UINT8 DramChannelPresent; |
| 322 | ex1047_STRUCT ex1047 ; |
| 323 | ex1048_STRUCT ex1048 ; |
| 324 | ex1060_STRUCT ex1060 ; |
| 325 | ex1061_STRUCT ex1061 ; |
| 326 | ex1062_STRUCT ex1062 ; |
| 327 | DCT_CHANNEL_INFO DctChannel; |
| 328 | D18F5x170_STRUCT D18F5x170; |
| 329 | ex1012_STRUCT ex1012 ; |
| 330 | ex1034_STRUCT ex1034 ; |
| 331 | |
| 332 | GfxGmcDctMemoryChannelInfoTN (&DctChannel, Gfx); |
| 333 | |
| 334 | DramChannelPresent = 0; |
| 335 | if (!DctChannel.D18F2x94_dct1.Field.DisDramInterface) { |
| 336 | DramChannelPresent |= GNB_GFX_DRAM_CH_1_PRESENT; |
| 337 | } |
| 338 | |
| 339 | if (!DctChannel.D18F2x94_dct0.Field.DisDramInterface) { |
| 340 | //if (channel 0 present) |
| 341 | //memps0_freq = extract frequency from DRAM Configuration High <D18F2x094_dct[0]>[4:0] encoding |
| 342 | //memps1_freq = extract frequency from Memory P-state Control Status <D18F2x2E0_dct[0]>[28:24] encoding |
| 343 | DramChannelPresent |= GNB_GFX_DRAM_CH_0_PRESENT; |
| 344 | memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct0.Field.MemClkFreq, GnbLibGetHeader (Gfx)); |
| 345 | memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx)); |
| 346 | } else { |
| 347 | //memps0_freq = extract frequency from DRAM Configuration High <D18F2x094_dct[1]>[4:0] encoding |
| 348 | //memps1_freq = extract frequency from Memory P-state Control Status <D18F2x2E0_dct[1]>[28:24] encoding |
| 349 | memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct1.Field.MemClkFreq, GnbLibGetHeader (Gfx)); |
| 350 | memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct1.Field.M1MemClkFreq, GnbLibGetHeader (Gfx)); |
| 351 | } |
| 352 | |
| 353 | GnbRegisterReadTN (D18F5x170_TYPE, D18F5x170_ADDRESS, &D18F5x170.Value, 0, GnbLibGetHeader (Gfx)); |
| 354 | if (D18F5x170.Field.MemPstateDis == 1) { |
| 355 | memps1_freq = memps0_freq; |
| 356 | } |
| 357 | |
| 358 | //scale_mp0 = sclk_max_freq / memps0_freq |
| 359 | //scale_mp1 = sclk_max_freq / memps1_freq |
| 360 | //Multiply it by 100 to avoid dealing with floating point values |
| 361 | scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq; |
| 362 | scale_mp1 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps1_freq; |
| 363 | |
| 364 | GnbRegisterReadTN (TYPE_GMM , 0x2774 , &ex1047.Value, 0, GnbLibGetHeader (Gfx)); |
| 365 | GnbRegisterReadTN (TYPE_GMM , 0x2778 , &ex1048.Value, 0, GnbLibGetHeader (Gfx)); |
| 366 | GnbRegisterReadTN (TYPE_GMM , 0x27f0 , &ex1060.Value, 0, GnbLibGetHeader (Gfx)); |
| 367 | GnbRegisterReadTN (TYPE_GMM , 0x27fc , &ex1061.Value, 0, GnbLibGetHeader (Gfx)); |
| 368 | |
| 369 | if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) { |
| 370 | ex1047.Field.ex1047_0 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trcd, DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100; |
| 371 | ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0; |
| 372 | ex1047.Field.ex1047_2 = (MIN ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd), |
| 373 | (DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd)) * scale_mp0) / 100; |
| 374 | ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2; |
| 375 | |
| 376 | ex1048.Field.ex1048_0 = (MIN (DctChannel.D18F2x204_dct0_mp0.Field.Trc, DctChannel.D18F2x204_dct1_mp0.Field.Trc) * scale_mp0) / 100; |
| 377 | ex1048.Field.ex1048_1 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trp, DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100; |
| 378 | ex1048.Field.ex1048_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp), |
| 379 | (DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp)) * scale_mp0) / 100; |
| 380 | ex1048.Field.ex1048_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO), |
| 381 | (DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO)) / 2) * scale_mp0) / 100; |
| 382 | |
| 383 | ex1060.Field.ex1060_0 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trcd, DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100; |
| 384 | ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0; |
| 385 | ex1060.Field.ex1060_2 = (MIN ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd), |
| 386 | (DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd)) * scale_mp1) / 100; |
| 387 | ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2; |
| 388 | |
| 389 | ex1061.Field.ex1061_0 = (MIN (DctChannel.D18F2x204_dct0_mp1.Field.Trc, DctChannel.D18F2x204_dct1_mp1.Field.Trc) * scale_mp1) / 100; |
| 390 | ex1061.Field.ex1061_1 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trp, DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100; |
| 391 | ex1061.Field.ex1061_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp), |
| 392 | (DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp)) * scale_mp1) / 100; |
| 393 | ex1061.Field.ex1061_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO), |
| 394 | (DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO)) / 2) * scale_mp1) / 100; |
| 395 | |
| 396 | } else if ((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) { |
| 397 | ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct0_mp0.Field.Trcd * scale_mp0) / 100; |
| 398 | ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0; |
| 399 | ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd) * scale_mp0) / 100; |
| 400 | ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2; |
| 401 | |
| 402 | ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct0_mp0.Field.Trc * scale_mp0) / 100; |
| 403 | ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct0_mp0.Field.Trp * scale_mp0) / 100; |
| 404 | ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp) * scale_mp0) / 100; |
| 405 | ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100; |
| 406 | |
| 407 | ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct0_mp1.Field.Trcd * scale_mp1) / 100; |
| 408 | ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0; |
| 409 | ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd) * scale_mp1) / 100; |
| 410 | ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2; |
| 411 | |
| 412 | ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct0_mp1.Field.Trc * scale_mp1) / 100; |
| 413 | ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct0_mp1.Field.Trp * scale_mp1) / 100; |
| 414 | ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp) * scale_mp1) / 100; |
| 415 | ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100; |
| 416 | |
| 417 | } else { |
| 418 | ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct1_mp0.Field.Trcd * scale_mp0) / 100; |
| 419 | ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0; |
| 420 | ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100; |
| 421 | ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2; |
| 422 | |
| 423 | ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct1_mp0.Field.Trc * scale_mp0) / 100; |
| 424 | ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct1_mp0.Field.Trp * scale_mp0) / 100; |
| 425 | ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100; |
| 426 | ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100; |
| 427 | |
| 428 | ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct1_mp1.Field.Trcd * scale_mp1) / 100; |
| 429 | ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0; |
| 430 | ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100; |
| 431 | ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2; |
| 432 | |
| 433 | ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct1_mp1.Field.Trc * scale_mp1) / 100; |
| 434 | ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct1_mp1.Field.Trp * scale_mp1) / 100; |
| 435 | ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100; |
| 436 | ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100; |
| 437 | } |
| 438 | |
| 439 | GnbRegisterWriteTN (TYPE_GMM , 0x2774 , &ex1047.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 440 | GnbRegisterWriteTN (TYPE_GMM , 0x2778 , &ex1048.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 441 | GnbRegisterWriteTN (TYPE_GMM , 0x27f0 , &ex1060.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 442 | GnbRegisterWriteTN (TYPE_GMM , 0x27fc , &ex1061.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 443 | ex1062.Field.ex1062_0 = GfxLibGetNumberOfSclkPerDramBurst (scale_mp0, GnbLibGetHeader (Gfx)); |
| 444 | ex1062.Field.ex1062_1 = GfxLibGetNumberOfSclkPerDramBurst (scale_mp1, GnbLibGetHeader (Gfx)); |
| 445 | GnbRegisterWriteTN (TYPE_GMM , 0x2808 , &ex1062.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 446 | |
| 447 | |
| 448 | //MC Performance settings base on memory channel configuration |
| 449 | //If 1 channel |
| 450 | ex1012.Value = 0x210; |
| 451 | ex1034.Value = 0x3; |
| 452 | if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) { |
| 453 | //If 2 channels |
| 454 | ex1012.Value = 0x1210; |
| 455 | ex1034.Value = 0xC3; |
| 456 | } |
| 457 | GnbRegisterWriteTN (TYPE_GMM , 0x2004 , &ex1012.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 458 | GnbRegisterWriteTN (TYPE_GMM , 0x2214 , &ex1034.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 459 | } |
| 460 | |
| 461 | /*----------------------------------------------------------------------------------------*/ |
| 462 | /** |
| 463 | * |
| 464 | * |
| 465 | * |
| 466 | * @param[in] Gfx Pointer to global GFX configuration |
| 467 | */ |
| 468 | |
| 469 | STATIC VOID |
| 470 | GfxGmcSecureGarlicAccessTN ( |
| 471 | IN GFX_PLATFORM_CONFIG *Gfx |
| 472 | ) |
| 473 | { |
| 474 | ex1064_STRUCT ex1064 ; |
| 475 | ex1065_STRUCT ex1065 ; |
| 476 | GMMx287C_STRUCT GMMx287C; |
| 477 | |
| 478 | ex1064.Value = (UINT32) (Gfx->UmaInfo.UmaBase >> 20); |
| 479 | GnbRegisterWriteTN (TYPE_GMM , 0x2868 , &ex1064.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 480 | ex1065.Value = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1); |
| 481 | GnbRegisterWriteTN (TYPE_GMM , 0x286c , &ex1065.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 482 | // Areag FB - 32K reserved by VBIOS for SBIOS to use |
| 483 | GMMx287C.Value = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 32 * 1024) >> 12); |
| 484 | GnbRegisterWriteTN (GMMx287C_TYPE, GMMx287C_ADDRESS, &GMMx287C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 485 | |
| 486 | } |
| 487 | |
| 488 | /*----------------------------------------------------------------------------------------*/ |
| 489 | /** |
| 490 | * Initialize C6 aperture location |
| 491 | * |
| 492 | * |
| 493 | * |
| 494 | * @param[in] Gfx Pointer to global GFX configuration |
| 495 | * |
| 496 | */ |
| 497 | STATIC VOID |
| 498 | GfxGmcInitializeC6LocationTN ( |
| 499 | IN GFX_PLATFORM_CONFIG *Gfx |
| 500 | ) |
| 501 | { |
| 502 | D18F2x118_STRUCT D18F2x118; |
| 503 | D18F1x44_STRUCT D18F1x44; |
| 504 | GMMx2870_STRUCT GMMx2870; |
| 505 | GMMx2874_STRUCT GMMx2874; |
| 506 | |
| 507 | // From D18F1x[144:140,44:40] DRAM Base/Limit, |
| 508 | // {DramBase[47:24], 00_0000h} <= address[47:0] <= {DramLimit[47:24], FF_FFFFh}. |
| 509 | GnbRegisterReadTN (D18F1x44_TYPE, D18F1x44_ADDRESS, &D18F1x44.Value, 0, GnbLibGetHeader (Gfx)); |
| 510 | // |
| 511 | // base 39:20, base = Dram Limit + 1 |
| 512 | // ex: system 256 MB on Node 0, D18F1x44.Field.DramLimit_39_24_ = 0xE (240MB -1) |
| 513 | // Node DRAM D18F1x[144:140,44:40] CC6DRAMRange D18F4x128 D18F1x120 D18F1x124 |
| 514 | // 0 256MB 0MB ~ 240 MB - 1 240 MB ~ 256 MB - 1 0 0 MB, 256 MB - 1 |
| 515 | // |
| 516 | |
| 517 | // base 39:20 |
| 518 | GMMx2870.Value = ((D18F1x44.Field.DramLimit_39_24_ + 1) << 4); |
| 519 | // top 39:20 |
| 520 | GMMx2874.Value = (((D18F1x44.Field.DramLimit_39_24_ + 1) << 24) + (16 * 0x100000) - 1) >> 20; |
| 521 | |
| 522 | // Check C6 enable, D18F2x118[CC6SaveEn] |
| 523 | GnbRegisterReadTN (TYPE_D18F2 , 0x118 , &D18F2x118.Value, 0, GnbLibGetHeader (Gfx)); |
| 524 | |
| 525 | if (D18F2x118.Field.CC6SaveEn) { |
| 526 | |
| 527 | GnbRegisterWriteTN (GMMx2874_TYPE, GMMx2874_ADDRESS, &GMMx2874.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 528 | GnbRegisterWriteTN (GMMx2870_TYPE, GMMx2870_ADDRESS, &GMMx2870.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 529 | } |
| 530 | } |
| 531 | |
| 532 | /*----------------------------------------------------------------------------------------*/ |
| 533 | /** |
| 534 | * Initialize GMC |
| 535 | * |
| 536 | * |
| 537 | * |
| 538 | * @param[in] Gfx Pointer to global GFX configuration |
| 539 | * |
| 540 | */ |
| 541 | |
| 542 | AGESA_STATUS |
| 543 | GfxGmcInitTN ( |
| 544 | IN GFX_PLATFORM_CONFIG *Gfx |
| 545 | ) |
| 546 | { |
| 547 | GMMx28D8_STRUCT GMMx28D8; |
| 548 | ex1017_STRUCT ex1017 ; |
| 549 | GNB_HANDLE *GnbHandle; |
| 550 | |
| 551 | IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Enter\n"); |
| 552 | GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); |
| 553 | ASSERT (GnbHandle != NULL); |
| 554 | GnbProcessTable ( |
| 555 | GnbHandle, |
| 556 | GfxGmcColockGatingDisableTN, |
| 557 | 0, |
| 558 | GNB_TABLE_FLAGS_FORCE_S3_SAVE, |
| 559 | GnbLibGetHeader (Gfx) |
| 560 | ); |
| 561 | GfxGmcInitializeSequencerTN (Gfx); |
| 562 | GfxGmcInitializeFbLocationTN (Gfx); |
| 563 | GfxGmcSecureGarlicAccessTN (Gfx); |
| 564 | GfxGmcInitializeC6LocationTN (Gfx); |
| 565 | GnbProcessTable ( |
| 566 | GnbHandle, |
| 567 | GfxGmcInitTableTN, |
| 568 | 0, |
| 569 | GNB_TABLE_FLAGS_FORCE_S3_SAVE, |
| 570 | GnbLibGetHeader (Gfx) |
| 571 | ); |
| 572 | if (Gfx->GmcClockGating) { |
| 573 | GnbProcessTable ( |
| 574 | GnbHandle, |
| 575 | GfxGmcColockGatingEnableTN, |
| 576 | 0, |
| 577 | GNB_TABLE_FLAGS_FORCE_S3_SAVE, |
| 578 | GnbLibGetHeader (Gfx) |
| 579 | ); |
| 580 | } |
| 581 | if (Gfx->UmaSteering == excel993 ) { |
| 582 | ex1017.Value = 0x2; |
| 583 | GnbRegisterWriteTN (TYPE_GMM , 0x206c , &ex1017.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 584 | } |
| 585 | IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx)); |
| 586 | if (Gfx->GmcLockRegisters) { |
| 587 | GnbRegisterReadTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, 0, GnbLibGetHeader (Gfx)); |
| 588 | GMMx28D8.Field.CRITICAL_REGS_LOCK = 1; |
| 589 | GnbRegisterWriteTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); |
| 590 | } |
| 591 | if (Gfx->GmcPowerGating != GmcPowerGatingDisabled) { |
| 592 | } |
| 593 | IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Exit\n"); |
| 594 | return AGESA_SUCCESS; |
| 595 | } |