Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 7 | #include <device/pciexp.h> |
| 8 | #include <device/pci_ids.h> |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 9 | #include <southbridge/intel/common/pciehp.h> |
| 10 | #include "chip.h" |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 11 | |
| 12 | static void pci_init(struct device *dev) |
| 13 | { |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 14 | struct southbridge_intel_i82801ix_config *config = dev->chip_info; |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 15 | |
| 16 | printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); |
| 17 | |
| 18 | /* Enable Bus Master */ |
Elyes HAOUAS | b9d2e22 | 2020-04-28 10:25:12 +0200 | [diff] [blame] | 19 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 20 | |
| 21 | /* Set Cache Line Size to 0x10 */ |
| 22 | // This has no effect but the OS might expect it |
| 23 | pci_write_config8(dev, 0x0c, 0x10); |
| 24 | |
Angel Pons | b82b431 | 2020-07-23 23:32:46 +0200 | [diff] [blame] | 25 | pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 26 | |
| 27 | /* Enable IO xAPIC on this PCIe port */ |
Angel Pons | 6740647 | 2020-06-08 11:13:42 +0200 | [diff] [blame] | 28 | pci_or_config32(dev, 0xd8, 1 << 7); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 29 | |
| 30 | /* Enable Backbone Clock Gating */ |
Angel Pons | 6740647 | 2020-06-08 11:13:42 +0200 | [diff] [blame] | 31 | pci_or_config32(dev, 0xe1, (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 32 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 33 | /* Set VC0 transaction class */ |
Angel Pons | 6740647 | 2020-06-08 11:13:42 +0200 | [diff] [blame] | 34 | pci_update_config32(dev, 0x114, ~0x000000ff, 1); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 35 | |
| 36 | /* Mask completion timeouts */ |
Angel Pons | 6740647 | 2020-06-08 11:13:42 +0200 | [diff] [blame] | 37 | pci_or_config32(dev, 0x148, 1 << 14); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 38 | |
| 39 | /* Lock R/WO Correctable Error Mask. */ |
Angel Pons | 6740647 | 2020-06-08 11:13:42 +0200 | [diff] [blame] | 40 | pci_update_config32(dev, 0x154, ~0, 0); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 41 | |
| 42 | /* Clear errors in status registers */ |
Angel Pons | 6740647 | 2020-06-08 11:13:42 +0200 | [diff] [blame] | 43 | pci_update_config16(dev, 0x06, ~0, 0); |
| 44 | pci_update_config16(dev, 0x1e, ~0, 0); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 45 | |
| 46 | /* Get configured ASPM state */ |
| 47 | const enum aspm_type apmc = pci_read_config32(dev, 0x50) & 3; |
| 48 | |
| 49 | /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ |
Angel Pons | 6740647 | 2020-06-08 11:13:42 +0200 | [diff] [blame] | 50 | if (apmc == PCIE_ASPM_BOTH) |
| 51 | pci_or_config32(dev, 0xe8, 1 << 1); |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 52 | |
| 53 | /* Enable expresscard hotplug events. */ |
| 54 | if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { |
Angel Pons | 6740647 | 2020-06-08 11:13:42 +0200 | [diff] [blame] | 55 | |
| 56 | pci_or_config32(dev, 0xd8, 1 << 30); |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 57 | pci_write_config16(dev, 0x42, 0x142); |
| 58 | } |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 59 | } |
| 60 | |
Elyes HAOUAS | 8aa5073 | 2018-05-13 13:34:58 +0200 | [diff] [blame] | 61 | static void pch_pciexp_scan_bridge(struct device *dev) |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 62 | { |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 63 | struct southbridge_intel_i82801ix_config *config = dev->chip_info; |
| 64 | |
Arthur Heymans | a560c71 | 2021-02-24 22:27:44 +0100 | [diff] [blame] | 65 | if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { |
| 66 | pciexp_hotplug_scan_bridge(dev); |
| 67 | } else { |
| 68 | /* Normal PCIe Scan */ |
| 69 | pciexp_scan_bridge(dev); |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 70 | } |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 71 | } |
| 72 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 73 | static struct device_operations device_ops = { |
| 74 | .read_resources = pci_bus_read_resources, |
| 75 | .set_resources = pci_dev_set_resources, |
| 76 | .enable_resources = pci_bus_enable_resources, |
| 77 | .init = pci_init, |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 78 | .scan_bus = pch_pciexp_scan_bridge, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 79 | .ops_pci = &pci_dev_ops_pci, |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 80 | }; |
| 81 | |
| 82 | /* 82801Ix (ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M) */ |
| 83 | static const unsigned short pci_device_ids[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 84 | PCI_DID_INTEL_82801IB_PCIE1, /* Port 1 */ |
| 85 | PCI_DID_INTEL_82801IB_PCIE2, /* Port 2 */ |
| 86 | PCI_DID_INTEL_82801IB_PCIE3, /* Port 3 */ |
| 87 | PCI_DID_INTEL_82801IB_PCIE4, /* Port 4 */ |
| 88 | PCI_DID_INTEL_82801IB_PCIE5, /* Port 5 */ |
| 89 | PCI_DID_INTEL_82801IB_PCIE6, /* Port 6 */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 90 | 0 |
| 91 | }; |
| 92 | static const struct pci_driver ich9_pcie __pci_driver = { |
| 93 | .ops = &device_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 94 | .vendor = PCI_VID_INTEL, |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 95 | .devices = pci_device_ids, |
| 96 | }; |