Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 2 | |
Angel Pons | 9b43b89 | 2020-06-21 13:11:10 +0200 | [diff] [blame] | 3 | #ifndef SOUTHBRIDGE_INTEL_I82801IX_I82801IX_H |
| 4 | #define SOUTHBRIDGE_INTEL_I82801IX_I82801IX_H |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 5 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 6 | #define DEFAULT_TBAR ((u8 *)0xfed1b000) |
Arthur Heymans | 2e464cf | 2018-06-13 00:07:09 +0200 | [diff] [blame] | 7 | |
Elyes Haouas | 35c3ae3b | 2022-10-27 12:25:12 +0200 | [diff] [blame] | 8 | #include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 9 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 10 | #if CONFIG(BOARD_EMULATION_QEMU_X86_Q35) |
Gerd Hoffmann | b142a51 | 2013-09-17 09:49:02 +0200 | [diff] [blame] | 11 | /* |
| 12 | * Qemu has the fw_cfg interface at 0x510. Move the pmbase to a |
| 13 | * non-conflicting address. No need to worry about speedstep, it |
| 14 | * is not supported by qemu and isn't enabled in the qemu config. |
| 15 | */ |
| 16 | # define DEFAULT_PMBASE 0x00000600 |
| 17 | #else |
| 18 | # define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */ |
| 19 | #endif |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 20 | #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) |
| 21 | #define DEFAULT_GPIOBASE 0x00000580 |
| 22 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 23 | #define APM_CNT 0xb2 |
| 24 | |
Timothy Pearson | 58649b0 | 2015-04-05 18:03:15 -0500 | [diff] [blame] | 25 | #define GP_IO_USE_SEL 0x00 |
| 26 | #define GP_IO_SEL 0x04 |
| 27 | #define GP_LVL 0x0c |
| 28 | #define GPO_BLINK 0x18 |
| 29 | #define GPI_INV 0x2c |
| 30 | #define GP_IO_USE_SEL2 0x30 |
| 31 | #define GP_IO_SEL2 0x34 |
| 32 | #define GP_LVL2 0x38 |
| 33 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 34 | #define DEBUG_PERIODIC_SMIS 0 |
| 35 | |
| 36 | #define MAINBOARD_POWER_OFF 0 |
| 37 | #define MAINBOARD_POWER_ON 1 |
| 38 | #define MAINBOARD_POWER_KEEP 2 |
| 39 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 40 | /* D31:F0 LPC bridge */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 41 | #define D31F0_ACPI_CNTL 0x44 |
| 42 | #define D31F0_GPIO_BASE 0x48 |
| 43 | #define D31F0_GPIO_CNTL 0x4c |
| 44 | #define D31F0_PIRQA_ROUT 0x60 |
| 45 | #define D31F0_PIRQB_ROUT 0x61 |
| 46 | #define D31F0_PIRQC_ROUT 0x62 |
| 47 | #define D31F0_PIRQD_ROUT 0x63 |
| 48 | #define D31F0_SERIRQ_CNTL 0x64 |
| 49 | #define D31F0_PIRQE_ROUT 0x68 |
| 50 | #define D31F0_PIRQF_ROUT 0x69 |
| 51 | #define D31F0_PIRQG_ROUT 0x6a |
| 52 | #define D31F0_PIRQH_ROUT 0x6b |
| 53 | #define D31F0_LPC_IODEC 0x80 |
| 54 | #define D31F0_LPC_EN 0x82 |
Angel Pons | 28d10a2 | 2020-08-10 13:39:25 +0200 | [diff] [blame] | 55 | #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
| 56 | #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
| 57 | #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
| 58 | #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
| 59 | #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
| 60 | #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
| 61 | #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
| 62 | #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
| 63 | #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
| 64 | #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 65 | #define D31F0_GEN1_DEC 0x84 |
Vladimir Serbinenko | 9d2cb7c | 2014-08-10 21:56:41 +0200 | [diff] [blame] | 66 | #define D31F0_GEN2_DEC 0x88 |
| 67 | #define D31F0_GEN3_DEC 0x8c |
| 68 | #define D31F0_GEN4_DEC 0x90 |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 69 | #define D31F0_C5_EXIT_TIMING 0xa8 |
| 70 | #define D31F0_CxSTATE_CNF 0xa9 |
| 71 | #define D31F0_C4TIMING_CNT 0xaa |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 72 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 73 | /* D31:F2 SATA */ |
| 74 | #define D31F2_IDE_TIM_PRI 0x40 |
| 75 | #define D31F2_IDE_TIM_SEC 0x42 |
| 76 | #define D31F2_SIDX 0xa0 |
| 77 | #define D31F2_SDAT 0xa4 |
| 78 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 79 | /* D30:F0 PCI-to-PCI bridge */ |
| 80 | #define D30F0_SMLT 0x1b |
| 81 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 82 | /* D28:F0-5 PCIe root ports */ |
| 83 | #define D28Fx_XCAP 0x42 |
| 84 | #define D28Fx_SLCAP 0x54 |
| 85 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 86 | /* PCI Configuration Space (D31:F3): SMBus */ |
| 87 | #define SMB_BASE 0x20 |
| 88 | #define HOSTC 0x40 |
| 89 | |
| 90 | /* HOSTC bits */ |
| 91 | #define I2C_EN (1 << 2) |
| 92 | #define SMB_SMI_EN (1 << 1) |
| 93 | #define HST_EN (1 << 0) |
| 94 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 95 | #define RCBA_V0CTL 0x0014 |
| 96 | #define RCBA_V1CAP 0x001c |
| 97 | #define RCBA_V1CTL 0x0020 |
| 98 | #define RCBA_V1STS 0x0026 |
| 99 | #define RCBA_PAT 0x0030 |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 100 | #define RCBA_CIR1 0x0088 |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 101 | #define RCBA_ESD 0x0104 |
| 102 | #define RCBA_ULD 0x0110 |
| 103 | #define RCBA_ULBA 0x0118 |
| 104 | #define RCBA_LCAP 0x01a4 |
| 105 | #define RCBA_LCTL 0x01a8 |
| 106 | #define RCBA_LSTS 0x01aa |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 107 | #define RCBA_CIR2 0x01f4 |
| 108 | #define RCBA_CIR3 0x01fc |
| 109 | #define RCBA_BCR 0x0220 |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 110 | #define RCBA_DMIC 0x0234 |
| 111 | #define RCBA_RPFN 0x0238 |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 112 | #define RCBA_CIR13 0x0f20 |
| 113 | #define RCBA_CIR5 0x1d40 |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 114 | #define RCBA_DMC 0x2010 |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 115 | #define RCBA_CIR6 0x2024 |
| 116 | #define RCBA_CIR7 0x2034 |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 117 | #define RCBA_HPTC 0x3404 |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 118 | #define GCS 0x3410 |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 119 | #define RCBA_BUC 0x3414 |
| 120 | #define RCBA_FD 0x3418 /* Function Disable, see below. */ |
| 121 | #define RCBA_CG 0x341c |
| 122 | #define RCBA_FDSW 0x3420 |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 123 | #define RCBA_CIR8 0x3430 |
| 124 | #define RCBA_CIR9 0x350c |
| 125 | #define RCBA_CIR10 0x352c |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 126 | #define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 127 | |
| 128 | #define BUC_LAND (1 << 5) /* LAN */ |
| 129 | #define FD_SAD2 (1 << 25) /* SATA #2 */ |
| 130 | #define FD_TTD (1 << 24) /* Thermal Throttle */ |
| 131 | #define FD_PE6D (1 << 21) /* PCIe root port 6 */ |
| 132 | #define FD_PE5D (1 << 20) /* PCIe root port 5 */ |
| 133 | #define FD_PE4D (1 << 19) /* PCIe root port 4 */ |
| 134 | #define FD_PE3D (1 << 18) /* PCIe root port 3 */ |
| 135 | #define FD_PE2D (1 << 17) /* PCIe root port 2 */ |
| 136 | #define FD_PE1D (1 << 16) /* PCIe root port 1 */ |
| 137 | #define FD_EHCI1D (1 << 15) /* EHCI #1 */ |
| 138 | #define FD_LBD (1 << 14) /* LPC bridge */ |
| 139 | #define FD_EHCI2D (1 << 13) /* EHCI #2 */ |
| 140 | #define FD_U5D (1 << 12) /* UHCI #5 */ |
| 141 | #define FD_U4D (1 << 11) /* UHCI #4 */ |
| 142 | #define FD_U3D (1 << 10) /* UHCI #3 */ |
| 143 | #define FD_U2D (1 << 9) /* UHCI #2 */ |
| 144 | #define FD_U1D (1 << 8) /* UHCI #1 */ |
| 145 | #define FD_U6D (1 << 7) /* UHCI #6 */ |
| 146 | #define FD_HDAD (1 << 4) /* HD audio */ |
| 147 | #define FD_SD (1 << 3) /* SMBus */ |
| 148 | #define FD_SAD1 (1 << 2) /* SATA #1 */ |
| 149 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 150 | #ifndef __ACPI__ |
| 151 | #ifndef __ASSEMBLER__ |
| 152 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 153 | #include <device/pci_ops.h> |
| 154 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 155 | static inline int lpc_is_mobile(const u16 devid) |
| 156 | { |
| 157 | return (devid == 0x2917) || (devid == 0x2919); |
| 158 | } |
| 159 | #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) |
| 160 | |
Kyösti Mälkki | 571b7b2 | 2019-07-08 23:25:05 +0300 | [diff] [blame] | 161 | void aseg_smm_lock(void); |
| 162 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 163 | void i82801ix_early_init(void); |
Angel Pons | 9f75f68 | 2020-06-21 13:14:40 +0200 | [diff] [blame] | 164 | void i82801ix_lpc_setup(void); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 165 | void i82801ix_dmi_setup(void); |
| 166 | void i82801ix_dmi_poll_vc1(void); |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 167 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 168 | #endif |
| 169 | #endif |
| 170 | |
| 171 | #endif |