Angel Pons | e67ab18 | 2020-04-04 18:51:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Hung-Te Lin | 7ece246 | 2019-08-05 03:08:57 +0800 | [diff] [blame] | 2 | |
| 3 | #include <device/mmio.h> |
| 4 | #include <edid.h> |
Hung-Te Lin | 7ece246 | 2019-08-05 03:08:57 +0800 | [diff] [blame] | 5 | #include <soc/addressmap.h> |
| 6 | #include <soc/ddp.h> |
Elyes HAOUAS | 29c4d1b | 2020-07-22 11:45:07 +0200 | [diff] [blame] | 7 | #include <types.h> |
Hung-Te Lin | 7ece246 | 2019-08-05 03:08:57 +0800 | [diff] [blame] | 8 | |
| 9 | #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) |
| 10 | #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) |
| 11 | |
| 12 | void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color) |
| 13 | { |
| 14 | write32(&disp_ovl[idx]->roi_size, height << 16 | width); |
| 15 | write32(&disp_ovl[idx]->roi_bgclr, color); |
| 16 | } |
| 17 | |
| 18 | void rdma_start(void) |
| 19 | { |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 20 | setbits32(&disp_rdma0->global_con, RDMA_ENGINE_EN); |
Hung-Te Lin | 7ece246 | 2019-08-05 03:08:57 +0800 | [diff] [blame] | 21 | } |
| 22 | |
| 23 | void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size) |
| 24 | { |
| 25 | u32 threshold; |
| 26 | u32 reg; |
| 27 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 28 | clrsetbits32(&disp_rdma0->size_con_0, 0x1FFF, width); |
| 29 | clrsetbits32(&disp_rdma0->size_con_1, 0xFFFFF, height); |
Hung-Te Lin | 7ece246 | 2019-08-05 03:08:57 +0800 | [diff] [blame] | 30 | |
| 31 | /* |
| 32 | * Enable FIFO underflow since DSI and DPI can't be blocked. Set the |
| 33 | * output threshold to 6 microseconds with 7/6 overhead to account for |
| 34 | * blanking, and with a pixel depth of 4 bytes: |
| 35 | */ |
| 36 | threshold = pixel_clk * 4 * 7 / 1000; |
| 37 | |
| 38 | if (threshold > fifo_size) |
| 39 | threshold = fifo_size; |
| 40 | |
| 41 | reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(fifo_size) | |
| 42 | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); |
| 43 | |
| 44 | write32(&disp_rdma0->fifo_con, reg); |
| 45 | } |
| 46 | |
| 47 | void color_start(u32 width, u32 height) |
| 48 | { |
| 49 | |
| 50 | write32(&disp_color0->width, width); |
| 51 | write32(&disp_color0->height, height); |
| 52 | write32(&disp_color0->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); |
| 53 | write32(&disp_color0->start, BIT(0)); |
| 54 | } |
| 55 | |
| 56 | void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height) |
| 57 | { |
| 58 | struct disp_ovl_regs *const ovl0 = disp_ovl[0]; |
| 59 | write32(&ovl0->layer[0].con, fmt << 12); |
| 60 | write32(&ovl0->layer[0].src_size, height << 16 | width); |
| 61 | write32(&ovl0->layer[0].pitch, (width * bpp) & 0xFFFF); |
| 62 | |
| 63 | /* Enable layer */ |
| 64 | write32(&ovl0->rdma[0].ctrl, BIT(0)); |
| 65 | write32(&ovl0->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); |
| 66 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 67 | setbits32(&ovl0->src_con, BIT(0)); |
Hung-Te Lin | 7ece246 | 2019-08-05 03:08:57 +0800 | [diff] [blame] | 68 | } |