Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <device/mmio.h> |
| 4 | #include <intelblocks/cfg.h> |
Ravi Sarawadi | 640b040 | 2022-10-14 12:28:02 -0700 | [diff] [blame] | 5 | #include <intelblocks/pcr.h> |
Kapil Porwal | 96c605f | 2022-11-29 18:21:53 +0530 | [diff] [blame] | 6 | #include <intelblocks/pmclib.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 7 | #include <intelpch/lockdown.h> |
Ravi Sarawadi | 640b040 | 2022-10-14 12:28:02 -0700 | [diff] [blame] | 8 | #include <soc/pcr_ids.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 9 | #include <soc/pm.h> |
| 10 | #include <stdint.h> |
| 11 | |
Ravi Sarawadi | 640b040 | 2022-10-14 12:28:02 -0700 | [diff] [blame] | 12 | /* PCR PSTH Control Register */ |
| 13 | #define PCR_PSTH_CTRLREG 0x1d00 |
| 14 | #define PSTH_CTRLREG_IOSFPTCGE (1 << 2) |
| 15 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 16 | static void pmc_lockdown_cfg(int chipset_lockdown) |
| 17 | { |
Kapil Porwal | 96c605f | 2022-11-29 18:21:53 +0530 | [diff] [blame] | 18 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 19 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 20 | /* PMSYNC */ |
Kapil Porwal | 96c605f | 2022-11-29 18:21:53 +0530 | [diff] [blame] | 21 | setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 22 | /* Lock down ABASE and sleep stretching policy */ |
Kapil Porwal | 96c605f | 2022-11-29 18:21:53 +0530 | [diff] [blame] | 23 | setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 24 | |
| 25 | if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) |
Kapil Porwal | 96c605f | 2022-11-29 18:21:53 +0530 | [diff] [blame] | 26 | setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK); |
| 27 | |
| 28 | if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) { |
| 29 | setbits32(pmcbase + GEN_PMCON_B, ST_FDIS_LOCK); |
| 30 | setbits32(pmcbase + SSML, SSML_SSL_EN); |
| 31 | setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK | |
| 32 | PM_CFG_XRAM_READ_DISABLE); |
| 33 | } |
| 34 | |
| 35 | /* Send PMC IPC to inform about PCI enumeration done */ |
| 36 | pmc_send_pci_enum_done(); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 37 | } |
| 38 | |
Ravi Sarawadi | 640b040 | 2022-10-14 12:28:02 -0700 | [diff] [blame] | 39 | static void soc_die_lockdown_cfg(void) |
| 40 | { |
| 41 | if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) |
| 42 | return; |
| 43 | |
| 44 | /* Enable IOSF Primary Trunk Clock Gating */ |
| 45 | pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE); |
| 46 | } |
| 47 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 48 | void soc_lockdown_config(int chipset_lockdown) |
| 49 | { |
| 50 | /* PMC lock down configuration */ |
| 51 | pmc_lockdown_cfg(chipset_lockdown); |
Ravi Sarawadi | 640b040 | 2022-10-14 12:28:02 -0700 | [diff] [blame] | 52 | /* SOC Die lock down configuration */ |
| 53 | soc_die_lockdown_cfg(); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 54 | } |