Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
| 6 | #include <drivers/i2c/designware/dw_i2c.h> |
Dinesh Gehlot | 166c75c7 | 2023-01-03 05:26:19 +0000 | [diff] [blame] | 7 | #include <gpio.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 8 | #include <intelblocks/cfg.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 9 | #include <intelblocks/gspi.h> |
| 10 | #include <intelblocks/power_limit.h> |
| 11 | #include <intelblocks/pcie_rp.h> |
| 12 | #include <intelblocks/tcss.h> |
| 13 | #include <soc/gpe.h> |
| 14 | #include <soc/pci_devs.h> |
| 15 | #include <soc/pmc.h> |
| 16 | #include <soc/serialio.h> |
| 17 | #include <soc/usb.h> |
| 18 | #include <stdint.h> |
| 19 | |
| 20 | /* Types of different SKUs */ |
| 21 | enum soc_intel_meteorlake_power_limits { |
| 22 | MTL_P_POWER_LIMITS_1, |
| 23 | MTL_P_POWER_LIMITS_2, |
| 24 | MTL_P_POWER_LIMITS_3, |
Sridhar Siricilla | ce4dc66 | 2022-11-14 08:47:34 +0530 | [diff] [blame] | 25 | MTL_P_POWER_LIMITS_4, |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 26 | MTL_POWER_LIMITS_COUNT |
| 27 | }; |
| 28 | |
| 29 | /* Types of display ports */ |
| 30 | enum ddi_ports { |
| 31 | DDI_PORT_A, |
| 32 | DDI_PORT_B, |
| 33 | DDI_PORT_C, |
| 34 | DDI_PORT_1, |
| 35 | DDI_PORT_2, |
| 36 | DDI_PORT_3, |
| 37 | DDI_PORT_4, |
| 38 | DDI_PORT_COUNT, |
| 39 | }; |
| 40 | |
| 41 | enum ddi_port_flags { |
| 42 | DDI_ENABLE_DDC = 1 << 0, |
| 43 | DDI_ENABLE_HPD = 1 << 1, |
| 44 | }; |
| 45 | |
Kapil Porwal | ae5ba37 | 2023-01-04 21:49:36 +0530 | [diff] [blame] | 46 | /* |
| 47 | * The Max Pkg Cstate |
| 48 | * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, |
| 49 | * 254 - CPU Default , 255 - Auto. |
| 50 | */ |
| 51 | enum pkgcstate_limit { |
| 52 | LIMIT_C0_C1 = 0, |
| 53 | LIMIT_C2 = 1, |
| 54 | LIMIT_C3 = 2, |
| 55 | LIMIT_C6 = 3, |
| 56 | LIMIT_C7 = 4, |
| 57 | LIMIT_C7S = 5, |
| 58 | LIMIT_C8 = 6, |
| 59 | LIMIT_C9 = 7, |
| 60 | LIMIT_C10 = 8, |
| 61 | LIMIT_CPUDEFAULT = 254, |
| 62 | LIMIT_AUTO = 255, |
| 63 | }; |
| 64 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 65 | /* Bit values for use in LpmStateEnableMask. */ |
| 66 | enum lpm_state_mask { |
| 67 | LPM_S0i2_0 = BIT(0), |
| 68 | LPM_S0i2_1 = BIT(1), |
| 69 | LPM_S0i2_2 = BIT(2), |
| 70 | LPM_S0i3_0 = BIT(3), |
| 71 | LPM_S0i3_1 = BIT(4), |
| 72 | LPM_S0i3_2 = BIT(5), |
| 73 | LPM_S0i3_3 = BIT(6), |
| 74 | LPM_S0i3_4 = BIT(7), |
| 75 | LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 |
| 76 | | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, |
| 77 | }; |
| 78 | |
| 79 | struct soc_intel_meteorlake_config { |
| 80 | |
| 81 | /* Common struct containing soc config data required by common code */ |
| 82 | struct soc_intel_common_config common_soc_config; |
| 83 | |
| 84 | /* Common struct containing power limits configuration information */ |
| 85 | struct soc_power_limits_config power_limits_config[MTL_POWER_LIMITS_COUNT]; |
| 86 | |
| 87 | /* Gpio group routed to each dword of the GPE0 block. Values are |
| 88 | * of the form PMC_GPP_[A:U] or GPD. */ |
| 89 | uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 90 | uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 91 | uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 92 | |
| 93 | /* Generic IO decode ranges */ |
| 94 | uint32_t gen1_dec; |
| 95 | uint32_t gen2_dec; |
| 96 | uint32_t gen3_dec; |
| 97 | uint32_t gen4_dec; |
| 98 | |
| 99 | /* Enable S0iX support */ |
| 100 | int s0ix_enable; |
| 101 | /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ |
| 102 | uint8_t tcss_d3_hot_disable; |
| 103 | /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ |
| 104 | uint8_t tcss_d3_cold_disable; |
| 105 | /* Enable DPTF support */ |
| 106 | int dptf_enable; |
| 107 | |
| 108 | /* Deep SX enable for both AC and DC */ |
| 109 | int deep_s3_enable_ac; |
| 110 | int deep_s3_enable_dc; |
| 111 | int deep_s5_enable_ac; |
| 112 | int deep_s5_enable_dc; |
| 113 | |
| 114 | /* Deep Sx Configuration |
| 115 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 116 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
| 117 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ |
| 118 | uint32_t deep_sx_config; |
| 119 | |
| 120 | /* TCC activation offset */ |
| 121 | uint32_t tcc_offset; |
| 122 | |
| 123 | /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. |
| 124 | * When enabled memory will be training at two different frequencies. |
Subrata Banik | 289f9a5 | 2023-01-20 21:38:05 +0530 | [diff] [blame] | 125 | * 0:Disabled, 1:Enabled |
| 126 | */ |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 127 | enum { |
Subrata Banik | 289f9a5 | 2023-01-20 21:38:05 +0530 | [diff] [blame] | 128 | SAGV_DISABLED, |
| 129 | SAGV_ENABLED, |
| 130 | } sagv; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 131 | |
| 132 | /* Rank Margin Tool. 1:Enable, 0:Disable */ |
Subrata Banik | 289f9a5 | 2023-01-20 21:38:05 +0530 | [diff] [blame] | 133 | uint8_t rmt; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 134 | |
| 135 | /* USB related */ |
| 136 | struct usb2_port_config usb2_ports[CONFIG_SOC_INTEL_USB2_DEV_MAX]; |
| 137 | struct usb3_port_config usb3_ports[CONFIG_SOC_INTEL_USB3_DEV_MAX]; |
| 138 | /* Wake Enable Bitmap for USB2 ports */ |
| 139 | uint16_t usb2_wake_enable_bitmap; |
| 140 | /* Wake Enable Bitmap for USB3 ports */ |
| 141 | uint16_t usb3_wake_enable_bitmap; |
| 142 | /* Program OC pins for TCSS */ |
| 143 | struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; |
John Zhao | 54a03e4 | 2022-08-03 20:07:03 -0700 | [diff] [blame] | 144 | /* Validate TBT firmware authenticated and loaded into IMR */ |
| 145 | bool tbt_authentication; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 146 | |
| 147 | /* SATA related */ |
| 148 | uint8_t sata_mode; |
| 149 | uint8_t sata_salp_support; |
| 150 | uint8_t sata_ports_enable[8]; |
| 151 | uint8_t sata_ports_dev_slp[8]; |
| 152 | |
| 153 | /* |
| 154 | * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. |
| 155 | * Default 0. Setting this to 1 disables the SATA Power Optimizer. |
| 156 | */ |
| 157 | uint8_t sata_pwr_optimize_disable; |
| 158 | |
| 159 | /* |
| 160 | * SATA Port Enable Dito Config. |
| 161 | * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). |
| 162 | */ |
| 163 | uint8_t sata_ports_enable_dito_config[8]; |
| 164 | |
| 165 | /* SataPortsDmVal is the DITO multiplier. Default is 15. */ |
| 166 | uint8_t sata_ports_dm_val[8]; |
| 167 | /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ |
| 168 | uint16_t sata_ports_dito_val[8]; |
| 169 | |
| 170 | /* Audio related */ |
| 171 | uint8_t pch_hda_dsp_enable; |
| 172 | |
| 173 | /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ |
| 174 | enum { |
| 175 | HDA_TMODE_2T = 0, |
| 176 | HDA_TMODE_4T = 2, |
| 177 | HDA_TMODE_8T = 3, |
| 178 | HDA_TMODE_16T = 4, |
| 179 | } pch_hda_idisp_link_tmode; |
| 180 | |
| 181 | /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */ |
| 182 | enum { |
| 183 | HDA_LINKFREQ_48MHZ = 3, |
| 184 | HDA_LINKFREQ_96MHZ = 4, |
| 185 | } pch_hda_idisp_link_frequency; |
| 186 | |
| 187 | bool pch_hda_idisp_codec_enable; |
| 188 | |
| 189 | struct pcie_rp_config pcie_rp[CONFIG_MAX_ROOT_PORTS]; |
| 190 | uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC]; |
| 191 | |
| 192 | /* Gfx related */ |
| 193 | enum { |
| 194 | IGD_SM_0MB = 0x00, |
| 195 | IGD_SM_32MB = 0x01, |
| 196 | IGD_SM_64MB = 0x02, |
| 197 | IGD_SM_96MB = 0x03, |
| 198 | IGD_SM_128MB = 0x04, |
| 199 | IGD_SM_160MB = 0x05, |
| 200 | IGD_SM_4MB = 0xF0, |
| 201 | IGD_SM_8MB = 0xF1, |
| 202 | IGD_SM_12MB = 0xF2, |
| 203 | IGD_SM_16MB = 0xF3, |
| 204 | IGD_SM_20MB = 0xF4, |
| 205 | IGD_SM_24MB = 0xF5, |
| 206 | IGD_SM_28MB = 0xF6, |
| 207 | IGD_SM_36MB = 0xF8, |
| 208 | IGD_SM_40MB = 0xF9, |
| 209 | IGD_SM_44MB = 0xFA, |
| 210 | IGD_SM_48MB = 0xFB, |
| 211 | IGD_SM_52MB = 0xFC, |
| 212 | IGD_SM_56MB = 0xFD, |
| 213 | IGD_SM_60MB = 0xFE, |
| 214 | } igd_dvmt50_pre_alloc; |
| 215 | uint8_t skip_ext_gfx_scan; |
| 216 | |
| 217 | /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ |
| 218 | uint8_t eist_enable; |
| 219 | |
| 220 | uint8_t PmTimerDisabled; |
| 221 | /* |
| 222 | * SerialIO device mode selection: |
| 223 | * PchSerialIoDisabled, |
| 224 | * PchSerialIoPci, |
| 225 | * PchSerialIoHidden, |
| 226 | * PchSerialIoLegacyUart, |
| 227 | * PchSerialIoSkipInit |
| 228 | */ |
| 229 | uint8_t serial_io_i2c_mode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
| 230 | uint8_t serial_io_gspi_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 231 | uint8_t serial_io_uart_mode[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 232 | /* |
| 233 | * GSPIn Default Chip Select Mode: |
| 234 | * 0:Hardware Mode, |
| 235 | * 1:Software Mode |
| 236 | */ |
| 237 | uint8_t serial_io_gspi_cs_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 238 | /* |
| 239 | * GSPIn Default Chip Select State: |
| 240 | * 0: Low, |
| 241 | * 1: High |
| 242 | */ |
| 243 | uint8_t serial_io_gspi_cs_state[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 244 | |
| 245 | /* CNVi BT Core Enable/Disable */ |
| 246 | bool cnvi_bt_core; |
| 247 | |
| 248 | /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ |
| 249 | bool cnvi_bt_audio_offload; |
| 250 | |
| 251 | /* |
| 252 | * These GPIOs will be programmed by the IOM to handle biasing of the |
| 253 | * Type-C aux (SBU) signals when certain alternate modes are used. |
| 254 | * `pad_auxn_dc` should be assigned to the GPIO pad providing negative |
| 255 | * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly, |
| 256 | * `pad_auxp_dc` should be assigned to the GPIO providing positive bias |
| 257 | * (name often contains `AUXP_DC` or `_AUX_P`). |
| 258 | */ |
| 259 | struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS]; |
| 260 | |
| 261 | /* |
| 262 | * SOC Aux orientation override: |
| 263 | * This is a bitfield that corresponds to up to 4 TCSS ports on MTL. |
| 264 | * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC. |
| 265 | * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines |
| 266 | * on the motherboard. |
| 267 | */ |
| 268 | uint16_t tcss_aux_ori; |
| 269 | |
| 270 | /* Connect Topology Command timeout value */ |
| 271 | uint16_t itbt_connect_topology_timeout_in_ms; |
| 272 | |
| 273 | /* |
| 274 | * Override GPIO PM configuration: |
| 275 | * 0: Use FSP default GPIO PM program, |
| 276 | * 1: coreboot to override GPIO PM program |
| 277 | */ |
| 278 | uint8_t gpio_override_pm; |
| 279 | |
| 280 | /* |
| 281 | * GPIO PM configuration: 0 to disable, 1 to enable power gating |
| 282 | * Bit 6-7: Reserved |
| 283 | * Bit 5: MISCCFG_GPSIDEDPCGEN |
| 284 | * Bit 4: MISCCFG_GPRCOMPCDLCGEN |
| 285 | * Bit 3: MISCCFG_GPRTCDLCGEN |
| 286 | * Bit 2: MISCCFG_GSXLCGEN |
| 287 | * Bit 1: MISCCFG_GPDPCGEN |
| 288 | * Bit 0: MISCCFG_GPDLCGEN |
| 289 | */ |
| 290 | uint8_t gpio_pm[TOTAL_GPIO_COMM]; |
| 291 | |
| 292 | /* DP config */ |
| 293 | /* |
| 294 | * Port config |
| 295 | * 0:Disabled, 1:eDP, 2:MIPI DSI |
| 296 | */ |
| 297 | uint8_t ddi_port_A_config; |
| 298 | uint8_t ddi_port_B_config; |
| 299 | |
| 300 | /* Enable(1)/Disable(0) HPD/DDC */ |
| 301 | uint8_t ddi_ports_config[DDI_PORT_COUNT]; |
| 302 | |
| 303 | /* Hybrid storage mode enable (1) / disable (0) |
| 304 | * This mode makes FSP detect Optane and NVME and set PCIe lane mode |
| 305 | * accordingly */ |
| 306 | uint8_t hybrid_storage_mode; |
| 307 | |
| 308 | /* |
| 309 | * Override CPU flex ratio value: |
| 310 | * CPU ratio value controls the maximum processor non-turbo ratio. |
| 311 | * Valid Range 0 to 63. |
| 312 | * |
| 313 | * In general descriptor provides option to set default cpu flex ratio. |
| 314 | * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. |
| 315 | * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. |
| 316 | * |
| 317 | * Only override CPU flex ratio if don't want to boot with non-turbo max. |
| 318 | */ |
| 319 | uint8_t cpu_ratio_override; |
| 320 | |
| 321 | /* |
| 322 | * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. |
| 323 | * Default 0. Setting this to 1 disables the DMI Power Optimizer. |
| 324 | */ |
| 325 | uint8_t dmi_pwr_optimize_disable; |
| 326 | |
| 327 | /* |
| 328 | * Enable(1)/Disable(0) CPU Replacement check. |
| 329 | * Default 0. Setting this to 1 to check CPU replacement. |
| 330 | */ |
| 331 | uint8_t cpu_replacement_check; |
| 332 | |
| 333 | /* ISA Serial Base selection. */ |
| 334 | enum { |
| 335 | ISA_SERIAL_BASE_ADDR_3F8, |
| 336 | ISA_SERIAL_BASE_ADDR_2F8, |
| 337 | } isa_serial_uart_base; |
| 338 | |
| 339 | /* |
| 340 | * Assign clock source port for GbE. 0: Disable, N-1: port number |
| 341 | * Default 0. |
| 342 | */ |
| 343 | uint8_t lan_clk; |
Wonkyu Kim | e5f6ff8 | 2022-10-13 13:34:27 -0700 | [diff] [blame] | 344 | |
| 345 | /* |
Kapil Porwal | ae5bc43 | 2023-01-04 22:03:02 +0530 | [diff] [blame] | 346 | * Enable or Disable Package C-state Demotion. |
| 347 | * Default is set to 0. |
| 348 | * Set this to 1 in order to disable Package C-state demotion. |
| 349 | */ |
| 350 | bool disable_package_c_state_demotion; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 351 | }; |
| 352 | |
| 353 | typedef struct soc_intel_meteorlake_config config_t; |
| 354 | |
| 355 | #endif |