Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpi.h> |
| 4 | #include <acpi/acpi_gnvs.h> |
| 5 | #include <acpi/acpigen.h> |
Arthur Heymans | d90154c | 2022-12-02 13:27:35 +0100 | [diff] [blame] | 6 | #include <arch/ioapic.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 7 | #include <device/mmio.h> |
| 8 | #include <arch/smp/mpspec.h> |
| 9 | #include <console/console.h> |
| 10 | #include <device/device.h> |
| 11 | #include <device/pci_ops.h> |
| 12 | #include <fw_config.h> |
| 13 | #include <intelblocks/cpulib.h> |
| 14 | #include <intelblocks/pmclib.h> |
| 15 | #include <intelblocks/acpi.h> |
| 16 | #include <soc/cpu.h> |
| 17 | #include <soc/iomap.h> |
| 18 | #include <soc/nvs.h> |
| 19 | #include <soc/pci_devs.h> |
| 20 | #include <soc/pm.h> |
| 21 | #include <soc/soc_chip.h> |
| 22 | #include <soc/systemagent.h> |
| 23 | #include <string.h> |
| 24 | #include <types.h> |
| 25 | |
| 26 | /* |
| 27 | * List of supported C-states in this processor. |
| 28 | */ |
| 29 | enum { |
| 30 | C_STATE_C0, /* 0 */ |
| 31 | C_STATE_C1, /* 1 */ |
| 32 | C_STATE_C1E, /* 2 */ |
| 33 | C_STATE_C6_SHORT_LAT, /* 3 */ |
| 34 | C_STATE_C6_LONG_LAT, /* 4 */ |
| 35 | C_STATE_C7_SHORT_LAT, /* 5 */ |
| 36 | C_STATE_C7_LONG_LAT, /* 6 */ |
| 37 | C_STATE_C7S_SHORT_LAT, /* 7 */ |
| 38 | C_STATE_C7S_LONG_LAT, /* 8 */ |
| 39 | C_STATE_C8, /* 9 */ |
| 40 | C_STATE_C9, /* 10 */ |
| 41 | C_STATE_C10, /* 11 */ |
| 42 | NUM_C_STATES |
| 43 | }; |
| 44 | |
| 45 | static const acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 46 | [C_STATE_C0] = {}, |
| 47 | [C_STATE_C1] = { |
| 48 | .latency = C1_LATENCY, |
| 49 | .power = C1_POWER, |
| 50 | .resource = MWAIT_RES(0, 0), |
| 51 | }, |
| 52 | [C_STATE_C1E] = { |
| 53 | .latency = C1_LATENCY, |
| 54 | .power = C1_POWER, |
| 55 | .resource = MWAIT_RES(0, 1), |
| 56 | }, |
| 57 | [C_STATE_C6_SHORT_LAT] = { |
| 58 | .latency = C6_LATENCY, |
| 59 | .power = C6_POWER, |
| 60 | .resource = MWAIT_RES(2, 0), |
| 61 | }, |
| 62 | [C_STATE_C6_LONG_LAT] = { |
| 63 | .latency = C6_LATENCY, |
| 64 | .power = C6_POWER, |
| 65 | .resource = MWAIT_RES(2, 1), |
| 66 | }, |
| 67 | [C_STATE_C7_SHORT_LAT] = { |
| 68 | .latency = C7_LATENCY, |
| 69 | .power = C7_POWER, |
| 70 | .resource = MWAIT_RES(3, 0), |
| 71 | }, |
| 72 | [C_STATE_C7_LONG_LAT] = { |
| 73 | .latency = C7_LATENCY, |
| 74 | .power = C7_POWER, |
| 75 | .resource = MWAIT_RES(3, 1), |
| 76 | }, |
| 77 | [C_STATE_C7S_SHORT_LAT] = { |
| 78 | .latency = C7_LATENCY, |
| 79 | .power = C7_POWER, |
| 80 | .resource = MWAIT_RES(3, 2), |
| 81 | }, |
| 82 | [C_STATE_C7S_LONG_LAT] = { |
| 83 | .latency = C7_LATENCY, |
| 84 | .power = C7_POWER, |
| 85 | .resource = MWAIT_RES(3, 3), |
| 86 | }, |
| 87 | [C_STATE_C8] = { |
| 88 | .latency = C8_LATENCY, |
| 89 | .power = C8_POWER, |
| 90 | .resource = MWAIT_RES(4, 0), |
| 91 | }, |
| 92 | [C_STATE_C9] = { |
| 93 | .latency = C9_LATENCY, |
| 94 | .power = C9_POWER, |
| 95 | .resource = MWAIT_RES(5, 0), |
| 96 | }, |
| 97 | [C_STATE_C10] = { |
| 98 | .latency = C10_LATENCY, |
| 99 | .power = C10_POWER, |
| 100 | .resource = MWAIT_RES(6, 0), |
| 101 | }, |
| 102 | }; |
| 103 | |
| 104 | static int cstate_set_non_s0ix[] = { |
| 105 | C_STATE_C1, |
| 106 | C_STATE_C6_LONG_LAT, |
| 107 | C_STATE_C7S_LONG_LAT |
| 108 | }; |
| 109 | |
| 110 | static int cstate_set_s0ix[] = { |
| 111 | C_STATE_C1, |
| 112 | C_STATE_C7S_LONG_LAT, |
| 113 | C_STATE_C10 |
| 114 | }; |
| 115 | |
| 116 | const acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
| 117 | { |
| 118 | static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), |
| 119 | ARRAY_SIZE(cstate_set_non_s0ix))]; |
| 120 | int *set; |
| 121 | int i; |
| 122 | |
| 123 | config_t *config = config_of_soc(); |
| 124 | |
| 125 | int is_s0ix_enable = config->s0ix_enable; |
| 126 | |
| 127 | if (is_s0ix_enable) { |
| 128 | *entries = ARRAY_SIZE(cstate_set_s0ix); |
| 129 | set = cstate_set_s0ix; |
| 130 | } else { |
| 131 | *entries = ARRAY_SIZE(cstate_set_non_s0ix); |
| 132 | set = cstate_set_non_s0ix; |
| 133 | } |
| 134 | |
| 135 | for (i = 0; i < *entries; i++) { |
| 136 | map[i] = cstate_map[set[i]]; |
| 137 | map[i].ctype = i + 1; |
| 138 | } |
| 139 | return map; |
| 140 | } |
| 141 | |
| 142 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 143 | { |
| 144 | config_t *config = config_of_soc(); |
| 145 | |
| 146 | if (config->eist_enable) |
| 147 | /* Generate P-state tables */ |
| 148 | generate_p_state_entries(core_id, cores_per_package); |
| 149 | } |
| 150 | |
| 151 | void soc_fill_fadt(acpi_fadt_t *fadt) |
| 152 | { |
| 153 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 154 | |
| 155 | config_t *config = config_of_soc(); |
| 156 | |
| 157 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 158 | fadt->pm_tmr_len = 4; |
| 159 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 160 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 161 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 162 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
Elyes Haouas | 987f1f4 | 2022-10-11 13:56:30 +0200 | [diff] [blame] | 163 | fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 164 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 165 | |
| 166 | if (config->s0ix_enable) |
| 167 | fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; |
| 168 | } |
| 169 | |
Eran Mitrani | 6d5d596 | 2023-01-03 14:29:35 -0800 | [diff] [blame] | 170 | static struct min_sleep_state min_pci_sleep_states[] = { |
| 171 | { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 }, |
| 172 | { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 }, |
| 173 | { PCI_DEVFN_DPTF, ACPI_DEVICE_SLEEP_D3 }, |
| 174 | { PCI_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, |
| 175 | { PCI_DEVFN_TBT0, ACPI_DEVICE_SLEEP_D3 }, |
| 176 | { PCI_DEVFN_TBT1, ACPI_DEVICE_SLEEP_D3 }, |
| 177 | { PCI_DEVFN_TBT2, ACPI_DEVICE_SLEEP_D3 }, |
| 178 | { PCI_DEVFN_TBT3, ACPI_DEVICE_SLEEP_D3 }, |
| 179 | { PCI_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 }, |
| 180 | { PCI_DEVFN_TCSS_XHCI, ACPI_DEVICE_SLEEP_D3 }, |
| 181 | { PCI_DEVFN_TCSS_XDCI, ACPI_DEVICE_SLEEP_D3 }, |
| 182 | { SA_DEVFN_TCSS_DMA0, ACPI_DEVICE_SLEEP_D3 }, |
| 183 | { SA_DEVFN_TCSS_DMA1, ACPI_DEVICE_SLEEP_D3 }, |
| 184 | { PCI_DEVFN_VMD, ACPI_DEVICE_SLEEP_D3 }, |
| 185 | { PCI_DEVFN_THC0, ACPI_DEVICE_SLEEP_D3 }, |
| 186 | { PCI_DEVFN_THC1, ACPI_DEVICE_SLEEP_D3 }, |
| 187 | { PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 }, |
| 188 | { PCI_DEVFN_USBOTG, ACPI_DEVICE_SLEEP_D3 }, |
| 189 | { PCI_DEVFN_SRAM, ACPI_DEVICE_SLEEP_D3 }, |
| 190 | { PCI_DEVFN_CNVI_WIFI, ACPI_DEVICE_SLEEP_D3 }, |
| 191 | { PCI_DEVFN_I2C0, ACPI_DEVICE_SLEEP_D3 }, |
| 192 | { PCI_DEVFN_I2C1, ACPI_DEVICE_SLEEP_D3 }, |
| 193 | { PCI_DEVFN_I2C2, ACPI_DEVICE_SLEEP_D3 }, |
| 194 | { PCI_DEVFN_I2C3, ACPI_DEVICE_SLEEP_D3 }, |
| 195 | { PCH_DEVFN_CSE, ACPI_DEVICE_SLEEP_D0 }, |
| 196 | { PCI_DEVFN_SATA, ACPI_DEVICE_SLEEP_D3 }, |
| 197 | { PCI_DEVFN_I2C4, ACPI_DEVICE_SLEEP_D3 }, |
| 198 | { PCI_DEVFN_I2C5, ACPI_DEVICE_SLEEP_D3 }, |
| 199 | { PCI_DEVFN_UART2, ACPI_DEVICE_SLEEP_D3 }, |
| 200 | { PCI_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 }, |
| 201 | { PCI_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 }, |
| 202 | { PCI_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 }, |
| 203 | { PCI_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 }, |
| 204 | { PCI_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 }, |
| 205 | { PCI_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 }, |
| 206 | { PCI_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 }, |
| 207 | { PCI_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 }, |
| 208 | { PCI_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 }, |
| 209 | { PCI_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 }, |
| 210 | { PCI_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 }, |
| 211 | { PCI_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 }, |
| 212 | { PCI_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 }, |
| 213 | { PCI_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 }, |
| 214 | { PCI_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 }, |
| 215 | { PCI_DEVFN_GSPI1, ACPI_DEVICE_SLEEP_D3 }, |
| 216 | { PCI_DEVFN_ESPI, ACPI_DEVICE_SLEEP_D0 }, |
| 217 | { PCH_DEVFN_PMC, ACPI_DEVICE_SLEEP_D0 }, |
| 218 | { PCI_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 }, |
| 219 | { PCI_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 }, |
| 220 | { PCI_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 }, |
| 221 | }; |
| 222 | |
| 223 | struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size) |
| 224 | { |
| 225 | *size = ARRAY_SIZE(min_pci_sleep_states); |
| 226 | return min_pci_sleep_states; |
| 227 | } |
| 228 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 229 | uint32_t soc_read_sci_irq_select(void) |
| 230 | { |
Dinesh Gehlot | 5778e06 | 2022-12-02 13:41:18 +0000 | [diff] [blame] | 231 | return read32p(soc_read_pmc_base() + IRQ_REG); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | static unsigned long soc_fill_dmar(unsigned long current) |
| 235 | { |
| 236 | unsigned long tmp; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 237 | const uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; |
| 238 | const bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; |
| 239 | |
| 240 | printk(BIOS_DEBUG, "%s - gfxvtbar:0x%llx 0x%x\n", |
| 241 | __func__, gfxvtbar, MCHBAR32(GFXVTBAR)); |
Dinesh Gehlot | 14a0876 | 2022-12-20 09:31:21 +0000 | [diff] [blame] | 242 | if (is_devfn_enabled(PCI_DEVFN_IGD) && gfxvtbar && gfxvten) { |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 243 | tmp = current; |
| 244 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
| 245 | current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); |
| 246 | |
| 247 | acpi_dmar_drhd_fixup(tmp, current); |
| 248 | } |
| 249 | |
| 250 | tmp = current; |
| 251 | current += acpi_create_dmar_drhd(current, |
| 252 | DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE_ADDRESS); |
Arthur Heymans | d90154c | 2022-12-02 13:27:35 +0100 | [diff] [blame] | 253 | current += acpi_create_dmar_ds_ioapic_from_hw(current, |
| 254 | IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 255 | V_P2SB_CFG_IBDF_FUNC); |
| 256 | current += acpi_create_dmar_ds_msi_hpet(current, |
| 257 | 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, |
| 258 | V_P2SB_CFG_HBDF_FUNC); |
| 259 | acpi_dmar_drhd_fixup(tmp, current); |
| 260 | |
| 261 | /* Add RMRR entry */ |
Dinesh Gehlot | 14a0876 | 2022-12-20 09:31:21 +0000 | [diff] [blame] | 262 | if (is_devfn_enabled(PCI_DEVFN_IGD) && gfxvtbar && gfxvten) { |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 263 | tmp = current; |
| 264 | current += acpi_create_dmar_rmrr(current, 0, |
| 265 | sa_get_gsm_base(), sa_get_tolud_base() - 1); |
| 266 | current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); |
| 267 | acpi_dmar_rmrr_fixup(tmp, current); |
| 268 | } |
| 269 | |
| 270 | tmp = current; |
| 271 | current += acpi_create_dmar_satc(current, ATC_REQUIRED, 0); |
| 272 | current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); |
| 273 | current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0); |
| 274 | acpi_dmar_satc_fixup(tmp, current); |
| 275 | |
| 276 | return current; |
| 277 | } |
| 278 | |
| 279 | unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, |
| 280 | struct acpi_rsdp *rsdp) |
| 281 | { |
| 282 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 283 | |
| 284 | /* |
| 285 | * Create DMAR table only if we have VT-d capability and FSP does not override its |
| 286 | * feature. |
| 287 | */ |
| 288 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || |
| 289 | !(MCHBAR32(GFXVTBAR) & VTBAR_ENABLED)) |
| 290 | return current; |
| 291 | |
| 292 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 293 | acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar); |
| 294 | current += dmar->header.length; |
| 295 | current = acpi_align_current(current); |
| 296 | acpi_add_table(rsdp, dmar); |
| 297 | |
| 298 | return current; |
| 299 | } |
| 300 | |
| 301 | void soc_fill_gnvs(struct global_nvs *gnvs) |
| 302 | { |
| 303 | config_t *config = config_of_soc(); |
| 304 | |
| 305 | /* Enable DPTF based on mainboard configuration */ |
| 306 | gnvs->dpte = config->dptf_enable; |
| 307 | |
| 308 | /* Set USB2/USB3 wake enable bitmaps. */ |
| 309 | gnvs->u2we = config->usb2_wake_enable_bitmap; |
| 310 | gnvs->u3we = config->usb3_wake_enable_bitmap; |
| 311 | } |
| 312 | |
| 313 | int soc_madt_sci_irq_polarity(int sci) |
| 314 | { |
| 315 | return MP_IRQ_POLARITY_HIGH; |
| 316 | } |