Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 2 | |
| 3 | #ifndef SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H |
| 4 | #define SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H |
| 5 | |
| 6 | /* PCI configuration registers */ |
| 7 | |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 8 | #define SPI_BIOS_CONTROL 0xdc |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 9 | |
Srinidhi N Kaushik | 6094908 | 2020-11-25 01:58:34 -0800 | [diff] [blame] | 10 | /* Extended Bios Support Registers */ |
| 11 | #define SPI_CFG_BAR1 0xe0 /* SPI BAR1 MMIO */ |
| 12 | |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 13 | /* Bit definitions for BIOS_CONTROL */ |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 14 | #define SPI_BIOS_CONTROL_WPD (1 << 0) |
| 15 | #define SPI_BIOS_CONTROL_LOCK_ENABLE (1 << 1) |
| 16 | #define SPI_BIOS_CONTROL_CACHE_DISABLE (1 << 2) |
| 17 | #define SPI_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) |
| 18 | #define SPI_BIOS_CONTROL_EISS (1 << 5) |
| 19 | #define SPI_BIOS_CONTROL_BILD (1 << 7) |
Angel Pons | 967753f | 2021-02-15 17:44:09 +0100 | [diff] [blame] | 20 | #define SPI_BIOS_CONTROL_SYNC_SS (1 << 8) |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 21 | #define SPI_BIOS_CONTROL_EXT_BIOS_ENABLE (1 << 27) |
| 22 | #define SPI_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE (1 << 28) |
| 23 | #define SPI_BIOS_CONTROL_EXT_BIOS_LIMIT(x) ((x) & ~(0xfff)) |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 24 | |
| 25 | /* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ |
| 26 | |
| 27 | #define SPIBAR_BFPREG 0x00 |
| 28 | #define SPIBAR_HSFSTS_CTL 0x04 |
| 29 | #define SPIBAR_FADDR 0x08 |
Barnali Sarkar | 4f6e341 | 2017-08-17 11:49:27 +0530 | [diff] [blame] | 30 | #define SPIBAR_DLOCK 0x0c |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 31 | #define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) |
| 32 | #define SPIBAR_FPR_BASE 0x84 |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 33 | #define SPIBAR_FPR(n) (0x84 + (4 * (n))) |
| 34 | #define SPIBAR_PREOP 0xa4 |
| 35 | #define SPIBAR_OPTYPE 0xa6 |
| 36 | #define SPIBAR_OPMENU_LOWER 0xa8 |
| 37 | #define SPIBAR_OPMENU_UPPER 0xac |
| 38 | #define SPIBAR_FDOC 0xb4 |
| 39 | #define SPIBAR_FDOD 0xb8 |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 40 | #define SPIBAR_PTINX 0xcc |
| 41 | #define SPIBAR_PTDATA 0xd0 |
| 42 | |
| 43 | /* Bit definitions for BFPREG (0x00) register */ |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 44 | #define SPIBAR_BFPREG_PRB_MASK 0x7fff |
| 45 | #define SPIBAR_BFPREG_PRL_SHIFT 16 |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 46 | #define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) |
| 47 | #define SPIBAR_BFPREG_SBRS (1 << 31) |
| 48 | |
| 49 | /* Bit definitions for HSFSTS_CTL (0x04) register */ |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 50 | #define SPIBAR_HSFSTS_FDBC_MASK (0x3f << 24) |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 51 | #define SPIBAR_HSFSTS_FDBC(n) (((n) << 24) & SPIBAR_HSFSTS_FDBC_MASK) |
| 52 | #define SPIBAR_HSFSTS_WET (1 << 21) |
| 53 | #define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17) |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 54 | #define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK) |
| 55 | |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 56 | /* Supported flash cycle types */ |
| 57 | #define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0) |
| 58 | #define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2) |
| 59 | #define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) |
| 60 | #define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) |
| 61 | #define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) |
| 62 | |
| 63 | #define SPIBAR_HSFSTS_FGO (1 << 16) |
| 64 | #define SPIBAR_HSFSTS_FLOCKDN (1 << 15) |
| 65 | #define SPIBAR_HSFSTS_FDV (1 << 14) |
| 66 | #define SPIBAR_HSFSTS_FDOPSS (1 << 13) |
Marc Jones | 051bf5d | 2021-03-30 12:16:09 -0600 | [diff] [blame] | 67 | #define SPIBAR_HSFSTS_PRR34_LOCKDN (1 << 12) |
Barnali Sarkar | 8e51319 | 2017-07-19 16:09:56 +0530 | [diff] [blame] | 68 | #define SPIBAR_HSFSTS_WRSDIS (1 << 11) |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 69 | #define SPIBAR_HSFSTS_SAF_CE (1 << 8) |
| 70 | #define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7) |
| 71 | #define SPIBAR_HSFSTS_SAF_LE (1 << 6) |
| 72 | #define SPIBAR_HSFSTS_SCIP (1 << 5) |
| 73 | #define SPIBAR_HSFSTS_SAF_DLE (1 << 4) |
| 74 | #define SPIBAR_HSFSTS_SAF_ERROR (1 << 3) |
| 75 | #define SPIBAR_HSFSTS_AEL (1 << 2) |
| 76 | #define SPIBAR_HSFSTS_FCERR (1 << 1) |
| 77 | #define SPIBAR_HSFSTS_FDONE (1 << 0) |
Subrata Banik | fa2854d | 2022-04-22 13:31:05 +0530 | [diff] [blame] | 78 | #define SPIBAR_HSFSTS_W1C_BITS 0x1ff |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 79 | |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 80 | /* Bit definitions for FADDR (0x08) register */ |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 81 | #define SPIBAR_FADDR_MASK 0x7ffffff |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 82 | |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 83 | /* Bit definitions for DLOCK (0x0c) register */ |
Barnali Sarkar | 4f6e341 | 2017-08-17 11:49:27 +0530 | [diff] [blame] | 84 | #define SPIBAR_DLOCK_PR0LOCKDN (1 << 8) |
| 85 | #define SPIBAR_DLOCK_PR1LOCKDN (1 << 9) |
| 86 | #define SPIBAR_DLOCK_PR2LOCKDN (1 << 10) |
| 87 | #define SPIBAR_DLOCK_PR3LOCKDN (1 << 11) |
| 88 | #define SPIBAR_DLOCK_PR4LOCKDN (1 << 12) |
| 89 | |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 90 | /* Maximum bytes of data that can fit in FDATAn (0x10) registers */ |
| 91 | #define SPIBAR_FDATA_FIFO_SIZE 0x40 |
| 92 | |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 93 | /* Bit definitions for FDOC (0xb4) register */ |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 94 | #define SPIBAR_FDOC_COMPONENT (1 << 12) |
| 95 | #define SPIBAR_FDOC_FDSI_1 (1 << 2) |
| 96 | |
| 97 | /* Flash Descriptor Component Section - Component 0 Density Bit Settings */ |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 98 | #define FLCOMP_C0DEN_MASK 0xf |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 99 | #define FLCOMP_C0DEN_8MB 4 |
| 100 | #define FLCOMP_C0DEN_16MB 5 |
| 101 | #define FLCOMP_C0DEN_32MB 6 |
| 102 | |
| 103 | /* Bit definitions for FPRn (0x84 + (4 * n)) registers */ |
| 104 | #define SPIBAR_FPR_WPE (1 << 31) /* Flash Write protected */ |
| 105 | #define SPIBAR_FPR_MAX 5 |
| 106 | |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 107 | /* Programmable values for OPMENU_LOWER(0xa8) & OPMENU_UPPER(0xac) register */ |
Elyes HAOUAS | 05498a2 | 2018-05-28 16:26:43 +0200 | [diff] [blame] | 108 | #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ |
| 109 | #define SPI_OPTYPE_0 0x01 /* Write, no address */ |
| 110 | #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ |
| 111 | #define SPI_OPTYPE_1 0x03 /* Write, address required */ |
| 112 | #define SPI_OPMENU_2 0x03 /* READ: Read Data */ |
| 113 | #define SPI_OPTYPE_2 0x02 /* Read, address required */ |
| 114 | #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ |
| 115 | #define SPI_OPTYPE_3 0x00 /* Read, no address */ |
| 116 | #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ |
| 117 | #define SPI_OPTYPE_4 0x03 /* Write, address required */ |
| 118 | #define SPI_OPMENU_5 0x9f /* RDID: Read ID */ |
| 119 | #define SPI_OPTYPE_5 0x00 /* Read, no address */ |
| 120 | #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ |
| 121 | #define SPI_OPTYPE_6 0x03 /* Write, address required */ |
| 122 | #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 123 | #define SPI_OPTYPE_7 0x02 /* Read, address required */ |
| 124 | #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ |
| 125 | (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) |
| 126 | #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ |
| 127 | (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) |
| 128 | #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ |
| 129 | (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ |
| 130 | (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ |
| 131 | (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) |
| 132 | #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ |
| 133 | |
Subrata Banik | d643165 | 2022-04-13 20:30:53 +0530 | [diff] [blame] | 134 | /* |
| 135 | * Register Offset of BIOS Vendor Specific Component Capabilities (VSCC) |
| 136 | * for Component 0 Register |
| 137 | */ |
| 138 | #define SPIBAR_SFDP0_VSCC0 0xc4 |
| 139 | #define SPIBAR_VSCC0_VCL (1 << 30) |
| 140 | |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 141 | /* Bit definitions for PTINX (0xcc) register */ |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 142 | #define SPIBAR_PTINX_COMP_0 (0 << 14) |
| 143 | #define SPIBAR_PTINX_COMP_1 (1 << 14) |
| 144 | #define SPIBAR_PTINX_HORD_SFDP (0 << 12) |
| 145 | #define SPIBAR_PTINX_HORD_PARAM (1 << 12) |
| 146 | #define SPIBAR_PTINX_HORD_JEDEC (2 << 12) |
| 147 | #define SPIBAR_PTINX_IDX_MASK 0xffc |
| 148 | |
| 149 | /* Register Offsets of BIOS Flash Program Registers */ |
Subrata Banik | e0b7423 | 2022-04-13 19:41:43 +0530 | [diff] [blame] | 150 | #define SPIBAR_RESET_LOCK 0xf0 |
| 151 | #define SPIBAR_RESET_CTRL 0xf4 |
| 152 | #define SPIBAR_RESET_DATA 0xf8 |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 153 | |
| 154 | /* Programmable values of Bit0 (SSL) of Set STRAP MSG LOCK (0xF0) Register */ |
| 155 | #define SPIBAR_RESET_LOCK_DISABLE 0 /* Set_Strap Lock(SSL) Bit 0 = 0 */ |
| 156 | #define SPIBAR_RESET_LOCK_ENABLE 1 /* Set_Strap Lock(SSL) Bit 0 = 1 */ |
| 157 | |
| 158 | /* Programmable values of Bit0(SSMS) of Set STRAP MSG Control (0xF4) Register*/ |
| 159 | #define SPIBAR_RESET_CTRL_SSMC 1 /* Set_Strap Mux Select(SSMS) Bit=1*/ |
| 160 | |
Angel Pons | 122cc8c | 2021-02-15 17:18:55 +0100 | [diff] [blame] | 161 | #define SPIBAR_HWSEQ_XFER_TIMEOUT_MS 5000 |
Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 162 | |
| 163 | void *fast_spi_get_bar(void); |
| 164 | |
| 165 | #endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H */ |