Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 5 | #include <device/pci_def.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 6 | #include <soc/iomap.h> |
| 7 | #include <soc/pci_devs.h> |
| 8 | #include <soc/romstage.h> |
| 9 | #include <soc/systemagent.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 10 | |
Angel Pons | 6f44874 | 2020-10-13 14:05:18 +0200 | [diff] [blame] | 11 | static void broadwell_setup_bars(void) |
| 12 | { |
| 13 | /* Set up all hardcoded northbridge BARs */ |
Angel Pons | 29924b2 | 2021-06-15 13:55:03 +0200 | [diff] [blame] | 14 | pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); |
| 15 | pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); |
| 16 | pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); |
Angel Pons | 6f44874 | 2020-10-13 14:05:18 +0200 | [diff] [blame] | 17 | |
Angel Pons | a8753e9 | 2021-04-17 14:34:37 +0200 | [diff] [blame] | 18 | mchbar_write32(EDRAMBAR, EDRAM_BASE_ADDRESS | 1); |
| 19 | mchbar_write32(GDXCBAR, GDXC_BASE_ADDRESS | 1); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 20 | |
| 21 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
Angel Pons | 29924b2 | 2021-06-15 13:55:03 +0200 | [diff] [blame] | 22 | pci_write_config8(HOST_BRIDGE, PAM0, 0x30); |
| 23 | pci_write_config8(HOST_BRIDGE, PAM1, 0x33); |
| 24 | pci_write_config8(HOST_BRIDGE, PAM2, 0x33); |
| 25 | pci_write_config8(HOST_BRIDGE, PAM3, 0x33); |
| 26 | pci_write_config8(HOST_BRIDGE, PAM4, 0x33); |
| 27 | pci_write_config8(HOST_BRIDGE, PAM5, 0x33); |
| 28 | pci_write_config8(HOST_BRIDGE, PAM6, 0x33); |
Angel Pons | 6f44874 | 2020-10-13 14:05:18 +0200 | [diff] [blame] | 29 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 30 | |
| 31 | void systemagent_early_init(void) |
| 32 | { |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 33 | const bool vtd_capable = |
Angel Pons | 29924b2 | 2021-06-15 13:55:03 +0200 | [diff] [blame] | 34 | !(pci_read_config32(HOST_BRIDGE, CAPID0_A) & VTD_DISABLE); |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 35 | |
Angel Pons | 6f44874 | 2020-10-13 14:05:18 +0200 | [diff] [blame] | 36 | broadwell_setup_bars(); |
| 37 | |
| 38 | /* Device enable: IGD and Mini-HD */ |
Angel Pons | 29924b2 | 2021-06-15 13:55:03 +0200 | [diff] [blame] | 39 | pci_write_config32(HOST_BRIDGE, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 40 | |
| 41 | if (vtd_capable) { |
| 42 | /* setup BARs: zeroize top 32 bits; set enable bit */ |
Angel Pons | a8753e9 | 2021-04-17 14:34:37 +0200 | [diff] [blame] | 43 | mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); |
| 44 | mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); |
| 45 | mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); |
| 46 | mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 47 | |
| 48 | /* set PRSCAPDIS, lock GFXVTBAR policy cfg registers */ |
| 49 | u32 reg32; |
Elyes Haouas | 878a99f | 2022-12-11 10:35:46 +0100 | [diff] [blame] | 50 | reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS); |
| 51 | write32p(GFXVT_BASE_ADDRESS + ARCHDIS, |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 52 | reg32 | DMAR_LCKDN | PRSCAPDIS); |
| 53 | /* lock VTVC0BAR policy cfg registers */ |
Elyes Haouas | 878a99f | 2022-12-11 10:35:46 +0100 | [diff] [blame] | 54 | reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS); |
| 55 | write32p(VTVC0_BASE_ADDRESS + ARCHDIS, |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 56 | reg32 | DMAR_LCKDN); |
| 57 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 58 | } |