Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 3 | #include <device/mmio.h> |
| 4 | #include <bootstate.h> |
| 5 | #include <cpu/x86/smm.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ops.h> |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 9 | #include <acpi/acpi_gnvs.h> |
| 10 | #include <amdblocks/amd_pci_util.h> |
| 11 | #include <amdblocks/aoac.h> |
| 12 | #include <amdblocks/acpimmio.h> |
| 13 | #include <amdblocks/acpi.h> |
| 14 | #include <amdblocks/smi.h> |
| 15 | #include <soc/southbridge.h> |
| 16 | #include <soc/smi.h> |
| 17 | #include <soc/amd_pci_int_defs.h> |
| 18 | #include <soc/pci_devs.h> |
| 19 | #include <agesa_headers.h> |
| 20 | #include <soc/acpi.h> |
| 21 | #include <soc/aoac_defs.h> |
| 22 | #include <soc/nvs.h> |
| 23 | #include <types.h> |
| 24 | |
| 25 | /* |
| 26 | * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME |
| 27 | * provides a visible association with the index, therefore helping |
| 28 | * maintainability of table. If a new index/name is defined in |
| 29 | * amd_pci_int_defs.h, just add the pair at the end of this table. |
| 30 | * Order is not important. |
| 31 | */ |
| 32 | static const struct irq_idx_name irq_association[] = { |
| 33 | { PIRQ_A, "INTA#" }, |
| 34 | { PIRQ_B, "INTB#" }, |
| 35 | { PIRQ_C, "INTC#" }, |
| 36 | { PIRQ_D, "INTD#" }, |
| 37 | { PIRQ_E, "INTE#" }, |
| 38 | { PIRQ_F, "INTF#" }, |
| 39 | { PIRQ_G, "INTG#" }, |
| 40 | { PIRQ_H, "INTH#" }, |
| 41 | { PIRQ_MISC, "Misc" }, |
| 42 | { PIRQ_MISC0, "Misc0" }, |
| 43 | { PIRQ_MISC1, "Misc1" }, |
| 44 | { PIRQ_MISC2, "Misc2" }, |
| 45 | { PIRQ_SIRQA, "Ser IRQ INTA" }, |
| 46 | { PIRQ_SIRQB, "Ser IRQ INTB" }, |
| 47 | { PIRQ_SIRQC, "Ser IRQ INTC" }, |
| 48 | { PIRQ_SIRQD, "Ser IRQ INTD" }, |
| 49 | { PIRQ_SCI, "SCI" }, |
| 50 | { PIRQ_SMBUS, "SMBUS" }, |
| 51 | { PIRQ_ASF, "ASF" }, |
| 52 | { PIRQ_HDA, "HDA" }, |
| 53 | { PIRQ_FC, "FC" }, |
| 54 | { PIRQ_PMON, "PerMon" }, |
| 55 | { PIRQ_SD, "SD" }, |
| 56 | { PIRQ_SDIO, "SDIOt" }, |
| 57 | { PIRQ_EHCI, "EHCI" }, |
| 58 | { PIRQ_XHCI, "XHCI" }, |
| 59 | { PIRQ_SATA, "SATA" }, |
| 60 | { PIRQ_GPIO, "GPIO" }, |
| 61 | { PIRQ_I2C0, "I2C0" }, |
| 62 | { PIRQ_I2C1, "I2C1" }, |
| 63 | { PIRQ_I2C2, "I2C2" }, |
| 64 | { PIRQ_I2C3, "I2C3" }, |
| 65 | { PIRQ_UART0, "UART0" }, |
| 66 | { PIRQ_UART1, "UART1" }, |
| 67 | }; |
| 68 | |
| 69 | const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) |
| 70 | { |
| 71 | *size = ARRAY_SIZE(irq_association); |
| 72 | return irq_association; |
| 73 | } |
| 74 | |
| 75 | static void fch_init_acpi_ports(void) |
| 76 | { |
| 77 | u32 reg; |
| 78 | |
| 79 | /* We use some of these ports in SMM regardless of whether or not |
| 80 | * ACPI tables are generated. Enable these ports indiscriminately. |
| 81 | */ |
| 82 | |
| 83 | pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); |
| 84 | pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); |
| 85 | pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); |
| 86 | pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); |
| 87 | /* CpuControl is in \_SB.CP00, 6 bytes */ |
| 88 | pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); |
| 89 | |
| 90 | if (CONFIG(HAVE_SMI_HANDLER)) { |
| 91 | /* APMC - SMI Command Port */ |
| 92 | pm_write16(PM_ACPI_SMI_CMD, APM_CNT); |
| 93 | configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); |
| 94 | |
| 95 | /* SMI on SlpTyp requires sending SMI before completion |
| 96 | * response of the I/O write. The BKDG also specifies |
| 97 | * clearing ForceStpClkRetry for SMI trapping. |
| 98 | */ |
| 99 | reg = pm_read32(PM_PCI_CTRL); |
| 100 | reg |= FORCE_SLPSTATE_RETRY; |
| 101 | reg &= ~FORCE_STPCLK_RETRY; |
| 102 | pm_write32(PM_PCI_CTRL, reg); |
| 103 | |
| 104 | /* Disable SlpTyp feature */ |
| 105 | reg = pm_read8(PM_RST_CTRL1); |
| 106 | reg &= ~SLPTYPE_CONTROL_EN; |
| 107 | pm_write8(PM_RST_CTRL1, reg); |
| 108 | |
| 109 | configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); |
| 110 | } else { |
| 111 | pm_write16(PM_ACPI_SMI_CMD, 0); |
| 112 | } |
| 113 | |
| 114 | /* Decode ACPI registers and enable standard features */ |
| 115 | pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | |
| 116 | PM_ACPI_GLOBAL_EN | |
| 117 | PM_ACPI_RTC_EN_EN | |
| 118 | PM_ACPI_TIMER_EN_EN); |
| 119 | } |
| 120 | |
| 121 | void fch_init(void *chip_info) |
| 122 | { |
| 123 | fch_init_acpi_ports(); |
| 124 | } |
| 125 | |
| 126 | static void set_sb_aoac(struct aoac_devs *aoac) |
| 127 | { |
| 128 | const struct device *sd, *sata; |
| 129 | |
| 130 | aoac->ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0); |
| 131 | aoac->ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1); |
| 132 | aoac->ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); |
| 133 | aoac->ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); |
| 134 | aoac->ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); |
| 135 | aoac->ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); |
| 136 | aoac->ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2); |
| 137 | aoac->xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3); |
| 138 | |
| 139 | /* Rely on these being in sync with devicetree */ |
| 140 | sd = pcidev_path_on_root(SD_DEVFN); |
| 141 | aoac->sd_e = sd && sd->enabled ? 1 : 0; |
| 142 | sata = pcidev_path_on_root(SATA_DEVFN); |
| 143 | aoac->st_e = sata && sata->enabled ? 1 : 0; |
| 144 | aoac->espi = 1; |
| 145 | } |
| 146 | |
| 147 | static void set_sb_gnvs(struct global_nvs *gnvs) |
| 148 | { |
| 149 | uintptr_t amdfw_rom; |
| 150 | uintptr_t xhci_fw; |
| 151 | uintptr_t fwaddr; |
| 152 | size_t fwsize; |
| 153 | |
| 154 | amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); |
Felix Held | 78ba98a | 2022-09-29 15:58:37 +0200 | [diff] [blame] | 155 | xhci_fw = read32p(amdfw_rom + XHCI_FW_SIG_OFFSET); |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 156 | |
Felix Held | 78ba98a | 2022-09-29 15:58:37 +0200 | [diff] [blame] | 157 | fwaddr = 2 + read16p(xhci_fw + XHCI_FW_ADDR_OFFSET + XHCI_FW_BOOTRAM_SIZE); |
| 158 | fwsize = read16p(xhci_fw + XHCI_FW_SIZE_OFFSET + XHCI_FW_BOOTRAM_SIZE); |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 159 | gnvs->fw00 = 0; |
| 160 | gnvs->fw01 = ((32 * KiB) << 16) + 0; |
| 161 | gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; |
| 162 | gnvs->fw03 = fwsize << 16; |
| 163 | |
Felix Held | ea6ee07 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 164 | /* TODO: This might break if the OS decides to re-allocate the PCI BARs. */ |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 165 | gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) |
| 166 | & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 167 | } |
| 168 | |
| 169 | void fch_final(void *chip_info) |
| 170 | { |
Felix Held | ea6ee07 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 171 | /* TODO: The AOAC states and EHCI/XHCI addresses should be moved out of GNVS */ |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 172 | struct global_nvs *gnvs = acpi_get_gnvs(); |
| 173 | if (gnvs) { |
| 174 | set_sb_aoac(&gnvs->aoac); |
| 175 | set_sb_gnvs(gnvs); |
| 176 | } |
| 177 | } |
| 178 | |
| 179 | /* |
| 180 | * Update the PCI devices with a valid IRQ number |
| 181 | * that is set in the mainboard PCI_IRQ structures. |
| 182 | */ |
| 183 | static void set_pci_irqs(void *unused) |
| 184 | { |
| 185 | /* Write PCI_INTR regs 0xC00/0xC01 */ |
| 186 | write_pci_int_table(); |
| 187 | |
| 188 | /* Write IRQs for all devicetree enabled devices */ |
| 189 | write_pci_cfg_irqs(); |
| 190 | } |
| 191 | |
| 192 | /* |
| 193 | * Hook this function into the PCI state machine |
| 194 | * on entry into BS_DEV_ENABLE. |
| 195 | */ |
| 196 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); |