Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <amdblocks/acpimmio.h> |
Felix Held | ba35f35 | 2022-10-18 20:43:00 +0200 | [diff] [blame] | 4 | #include <amdblocks/aoac.h> |
Felix Held | 02b61ae | 2022-08-18 19:06:50 +0200 | [diff] [blame] | 5 | #include <amdblocks/i2c.h> |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 6 | #include <amdblocks/lpc.h> |
| 7 | #include <amdblocks/pmlib.h> |
| 8 | #include <amdblocks/reset.h> |
| 9 | #include <amdblocks/smbus.h> |
| 10 | #include <amdblocks/spi.h> |
Felix Held | 8ebdbbc | 2022-10-18 20:52:42 +0200 | [diff] [blame] | 11 | #include <amdblocks/uart.h> |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 12 | #include <soc/southbridge.h> |
| 13 | #include <types.h> |
| 14 | |
Felix Held | 02b61ae | 2022-08-18 19:06:50 +0200 | [diff] [blame] | 15 | #include "chip.h" |
| 16 | |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 17 | static void sb_lpc_decode(void) |
| 18 | { |
| 19 | u32 tmp = 0; |
| 20 | |
| 21 | /* Enable I/O decode to LPC bus */ |
| 22 | tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 |
| 23 | | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 |
| 24 | | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 |
| 25 | | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 |
| 26 | | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 |
| 27 | | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 |
| 28 | | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 |
| 29 | | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 |
| 30 | | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 |
| 31 | | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT |
| 32 | | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT |
| 33 | | DECODE_ENABLE_ADLIB_PORT; |
| 34 | |
| 35 | /* Decode SIOs at 2E/2F and 4E/4F */ |
| 36 | if (CONFIG(STONEYRIDGE_LEGACY_FREE)) |
| 37 | tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; |
| 38 | |
| 39 | lpc_enable_decode(tmp); |
| 40 | } |
| 41 | |
| 42 | static void setup_spread_spectrum(int *reboot) |
| 43 | { |
| 44 | uint16_t rstcfg = pm_read16(PWR_RESET_CFG); |
| 45 | |
| 46 | rstcfg &= ~TOGGLE_ALL_PWR_GOOD; |
| 47 | pm_write16(PWR_RESET_CFG, rstcfg); |
| 48 | |
| 49 | uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); |
| 50 | |
| 51 | if (cntl1 & CG1PLL_FBDIV_TEST) { |
| 52 | printk(BIOS_DEBUG, "Spread spectrum is ready\n"); |
| 53 | misc_write32(MISC_CGPLL_CONFIG1, |
| 54 | misc_read32(MISC_CGPLL_CONFIG1) | |
| 55 | CG1PLL_SPREAD_SPECTRUM_ENABLE); |
| 56 | |
| 57 | return; |
| 58 | } |
| 59 | |
| 60 | printk(BIOS_DEBUG, "Setting up spread spectrum\n"); |
| 61 | |
| 62 | uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); |
| 63 | cfg6 &= ~CG1PLL_LF_MODE_MASK; |
| 64 | cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; |
| 65 | misc_write32(MISC_CGPLL_CONFIG6, cfg6); |
| 66 | |
| 67 | uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); |
| 68 | cfg3 &= ~CG1PLL_REFDIV_MASK; |
| 69 | cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; |
| 70 | cfg3 &= ~CG1PLL_FBDIV_MASK; |
| 71 | cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; |
| 72 | misc_write32(MISC_CGPLL_CONFIG3, cfg3); |
| 73 | |
| 74 | uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); |
| 75 | cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; |
| 76 | cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; |
| 77 | misc_write32(MISC_CGPLL_CONFIG5, cfg5); |
| 78 | |
| 79 | uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); |
| 80 | cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; |
| 81 | cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; |
| 82 | cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; |
| 83 | cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) |
| 84 | & SS_STEP_SIZE_DSFRAC_MASK; |
| 85 | misc_write32(MISC_CGPLL_CONFIG4, cfg4); |
| 86 | |
| 87 | rstcfg |= TOGGLE_ALL_PWR_GOOD; |
| 88 | pm_write16(PWR_RESET_CFG, rstcfg); |
| 89 | |
| 90 | cntl1 |= CG1PLL_FBDIV_TEST; |
| 91 | misc_write32(MISC_CLK_CNTL1, cntl1); |
| 92 | |
| 93 | *reboot = 1; |
| 94 | } |
| 95 | |
| 96 | static void setup_misc(int *reboot) |
| 97 | { |
| 98 | /* Undocumented register */ |
| 99 | uint32_t reg = misc_read32(0x50); |
| 100 | if (!(reg & BIT(16))) { |
| 101 | reg |= BIT(16); |
| 102 | |
| 103 | misc_write32(0x50, reg); |
| 104 | *reboot = 1; |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | /* Before console init */ |
| 109 | void bootblock_fch_early_init(void) |
| 110 | { |
| 111 | int reboot = 0; |
| 112 | |
| 113 | /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access |
| 114 | the GPIO registers. */ |
| 115 | enable_acpimmio_decode_pm04(); |
| 116 | lpc_enable_rom(); |
Felix Held | f7d86f2 | 2022-08-17 21:38:07 +0200 | [diff] [blame] | 117 | lpc_early_init(); |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 118 | lpc_enable_port80(); |
| 119 | sb_lpc_decode(); |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 120 | fch_spi_early_init(); |
| 121 | fch_smbus_init(); |
| 122 | fch_enable_cf9_io(); |
| 123 | setup_spread_spectrum(&reboot); |
| 124 | setup_misc(&reboot); |
| 125 | |
| 126 | if (reboot) |
| 127 | warm_reset(); |
| 128 | |
| 129 | fch_enable_legacy_io(); |
| 130 | enable_aoac_devices(); |
| 131 | |
Felix Held | f1a03b1 | 2022-10-18 19:48:41 +0200 | [diff] [blame] | 132 | if (CONFIG(AMD_SOC_CONSOLE_UART)) |
| 133 | set_uart_config(CONFIG_UART_FOR_CONSOLE); |
| 134 | |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 135 | /* disable the keyboard reset function before mainboard GPIO setup */ |
| 136 | if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) |
| 137 | fch_disable_kb_rst(); |
| 138 | } |
| 139 | |
| 140 | /* After console init */ |
| 141 | void bootblock_fch_init(void) |
| 142 | { |
Felix Held | 02b61ae | 2022-08-18 19:06:50 +0200 | [diff] [blame] | 143 | /* |
| 144 | * This call (sb_reset_i2c_peripherals) was originally early at |
| 145 | * bootblock_c_entry, but had to be moved here. There was an |
| 146 | * unexplained delay in the middle of the i2c transaction when |
| 147 | * we had it in bootblock_c_entry. Moving it to this point |
| 148 | * (or adding delays) fixes the issue. It seems like the processor |
| 149 | * just pauses but we don't know why. |
| 150 | */ |
| 151 | reset_i2c_peripherals(); |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 152 | pm_set_power_failure_state(); |
| 153 | fch_print_pmxc0_status(); |
Felix Held | 02b61ae | 2022-08-18 19:06:50 +0200 | [diff] [blame] | 154 | /* Initialize any early i2c buses. */ |
| 155 | i2c_soc_early_init(); |
Felix Held | 2d020e1 | 2021-12-15 20:52:10 +0100 | [diff] [blame] | 156 | show_spi_speeds_and_modes(); |
| 157 | } |
| 158 | |
| 159 | void fch_clk_output_48Mhz(u32 osc) |
| 160 | { |
| 161 | u32 ctrl; |
| 162 | |
| 163 | /* |
| 164 | * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) |
| 165 | * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. |
| 166 | */ |
| 167 | ctrl = misc_read32(MISC_CLK_CNTL1); |
| 168 | |
| 169 | switch (osc) { |
| 170 | case 1: |
| 171 | ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; |
| 172 | break; |
| 173 | case 2: |
| 174 | ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; |
| 175 | break; |
| 176 | default: |
| 177 | return; /* do nothing if invalid */ |
| 178 | } |
| 179 | misc_write32(MISC_CLK_CNTL1, ctrl); |
| 180 | } |