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Angel Pons8a3453f2020-04-02 23:48:19 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Werner Zeh6c571462016-07-05 07:16:34 +02002
3#ifndef _SIEMENS_NC_FPGA_H_
4#define _SIEMENS_NC_FPGA_H_
5
Elyes HAOUASc4e41932018-11-01 11:29:50 +01006#include <stdint.h>
7
Mario Scheithauerc4ff1de2017-06-12 10:02:10 +02008#define NC_MAGIC_OFFSET 0x020
9#define NC_FPGA_MAGIC 0x4E433746
10#define NC_CAP1_OFFSET 0x080
11#define NC_CAP1_DSAVE_NMI_DELAY 0x008
12#define NC_CAP1_BL_BRIGHTNESS_CTRL 0x010
13#define NC_CAP1_FAN_CTRL 0x080
14#define NC_CAP1_TEMP_MON 0x100
15#define NC_DSAVE_OFFSET 0x58
Werner Zehf1f67c32017-10-19 07:21:54 +020016#define NC_DIAG_CTRL_OFFSET 0x60
17#define NC_DIAG_FW_DONE 0x10000
Mario Scheithauerc4ff1de2017-06-12 10:02:10 +020018#define NC_BL_BRIGHTNESS_OFFSET 0x88
19#define NC_BL_PWM_OFFSET 0x8C
Werner Zeh42b88352021-11-16 07:31:44 +010020#define NC_FPGA_POST_OFFSET 0xE0
Mario Scheithauerc4ff1de2017-06-12 10:02:10 +020021#define NC_FANMON_CTRL_OFFSET 0x400
Werner Zeh6c571462016-07-05 07:16:34 +020022
Werner Zeh2db79222017-07-05 15:52:52 +020023#define MAX_NUM_SENSORS 8
Werner Zeh6c571462016-07-05 07:16:34 +020024
25typedef struct {
26 uint16_t rmin;
27 uint16_t rmax;
28 uint16_t nmin;
29 uint16_t nmax;
30} temp_cc_t;
31
32typedef struct {
33 uint16_t res0;
34 uint8_t sensornum;
35 uint8_t res1;
36 uint32_t sensordelay;
37 uint32_t res2[4];
38 temp_cc_t sensorcfg[8];
39 uint32_t res3[4];
40 uint8_t sensorselect;
41 uint8_t res4[3];
42 uint16_t t_warn;
43 uint16_t t_crit;
44 uint16_t res5;
45 uint8_t res6[2];
46 uint32_t samplingtime;
47 uint16_t setpoint;
48 uint8_t hystctrl;
49 uint8_t res7;
50 uint16_t kp;
51 uint16_t ki;
52 uint16_t kd;
Werner Zehc38ab852017-07-27 13:48:18 +020053 uint16_t fanmin;
54 uint16_t res8;
Werner Zeh6c571462016-07-05 07:16:34 +020055 uint16_t fanmax;
56 uint16_t hystval;
57 uint16_t hystthreshold;
58 uint16_t res9[4];
59 uint32_t fanmon;
Stefan Reinauer6a001132017-07-13 02:20:27 +020060} __packed fan_ctrl_t;
Werner Zeh6c571462016-07-05 07:16:34 +020061
Werner Zeh42b88352021-11-16 07:31:44 +010062void nc_fpga_post(uint8_t value);
63void nc_fpga_remap(uint32_t new_mmio);
64
Werner Zeh6c571462016-07-05 07:16:34 +020065#endif /* _SIEMENS_NC_FPGA_H_ */