Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> |
| 5 | * Copyright (C) 2009 coresystems GmbH |
| 6 | * Copyright (C) 2013 Vladimir Serbinenko |
Frans Hendriks | e48be35 | 2019-06-19 11:01:27 +0200 | [diff] [blame] | 7 | * Copyright (C) 2018-2019 Eltan B.V. |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <arch/io.h> |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 20 | #include <console/console.h> |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 21 | #include <device/smbus_def.h> |
Elyes HAOUAS | ab89edb | 2019-05-15 21:10:44 +0200 | [diff] [blame] | 22 | #include <types.h> |
| 23 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 24 | #include "smbus.h" |
| 25 | |
| 26 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 27 | #if CONFIG(DEBUG_SMBUS) |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 28 | #define dprintk(args...) printk(BIOS_DEBUG, ##args) |
| 29 | #else |
| 30 | #define dprintk(args...) do {} while (0) |
| 31 | #endif |
| 32 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 33 | /* I801 command constants */ |
| 34 | #define I801_QUICK (0 << 2) |
| 35 | #define I801_BYTE (1 << 2) |
| 36 | #define I801_BYTE_DATA (2 << 2) |
| 37 | #define I801_WORD_DATA (3 << 2) |
| 38 | #define I801_BLOCK_DATA (5 << 2) |
| 39 | #define I801_I2C_BLOCK_DATA (6 << 2) /* ICH5 and later */ |
| 40 | |
| 41 | /* I801 Host Control register bits */ |
| 42 | #define SMBHSTCNT_INTREN (1 << 0) |
| 43 | #define SMBHSTCNT_KILL (1 << 1) |
| 44 | #define SMBHSTCNT_LAST_BYTE (1 << 5) |
| 45 | #define SMBHSTCNT_START (1 << 6) |
| 46 | #define SMBHSTCNT_PEC_EN (1 << 7) /* ICH3 and later */ |
| 47 | |
| 48 | /* I801 Hosts Status register bits */ |
| 49 | #define SMBHSTSTS_BYTE_DONE (1 << 7) |
| 50 | #define SMBHSTSTS_INUSE_STS (1 << 6) |
| 51 | #define SMBHSTSTS_SMBALERT_STS (1 << 5) |
| 52 | #define SMBHSTSTS_FAILED (1 << 4) |
| 53 | #define SMBHSTSTS_BUS_ERR (1 << 3) |
| 54 | #define SMBHSTSTS_DEV_ERR (1 << 2) |
| 55 | #define SMBHSTSTS_INTR (1 << 1) |
| 56 | #define SMBHSTSTS_HOST_BUSY (1 << 0) |
| 57 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 58 | /* For SMBXMITADD register. */ |
| 59 | #define XMIT_WRITE(dev) (((dev) << 1) | 0) |
| 60 | #define XMIT_READ(dev) (((dev) << 1) | 1) |
| 61 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 62 | #define SMBUS_TIMEOUT (10 * 1000 * 100) |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 63 | #define SMBUS_BLOCK_MAXLEN 32 |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 64 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 65 | /* block_cmd_loop flags */ |
| 66 | #define BLOCK_READ 0 |
| 67 | #define BLOCK_WRITE (1 << 0) |
| 68 | #define BLOCK_I2C (1 << 1) |
| 69 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 70 | static void smbus_delay(void) |
| 71 | { |
| 72 | inb(0x80); |
| 73 | } |
| 74 | |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 75 | static int host_completed(u8 status) |
| 76 | { |
| 77 | if (status & SMBHSTSTS_HOST_BUSY) |
| 78 | return 0; |
Kyösti Mälkki | 44206e3 | 2019-02-26 17:17:24 +0200 | [diff] [blame] | 79 | |
| 80 | /* These status bits do not imply completion of transaction. */ |
| 81 | status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | |
| 82 | SMBHSTSTS_SMBALERT_STS); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 83 | return status != 0; |
| 84 | } |
| 85 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 86 | static int recover_master(int smbus_base, int ret) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 87 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 88 | /* TODO: Depending of the failure, drive KILL transaction |
| 89 | * or force soft reset on SMBus master controller. |
| 90 | */ |
| 91 | printk(BIOS_ERR, "SMBus: Fatal master timeout (%d)\n", ret); |
| 92 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 93 | } |
| 94 | |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 95 | static int cb_err_from_stat(u8 status) |
| 96 | { |
Kyösti Mälkki | 44206e3 | 2019-02-26 17:17:24 +0200 | [diff] [blame] | 97 | /* These status bits do not imply errors. */ |
| 98 | status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | |
| 99 | SMBHSTSTS_SMBALERT_STS); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 100 | |
| 101 | if (status == SMBHSTSTS_INTR) |
| 102 | return 0; |
| 103 | |
| 104 | return SMBUS_ERROR; |
| 105 | } |
| 106 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 107 | static int setup_command(unsigned int smbus_base, u8 ctrl, u8 xmitadd) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 108 | { |
| 109 | unsigned int loops = SMBUS_TIMEOUT; |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 110 | u8 host_busy; |
| 111 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 112 | do { |
| 113 | smbus_delay(); |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 114 | host_busy = inb(smbus_base + SMBHSTSTAT) & SMBHSTSTS_HOST_BUSY; |
| 115 | } while (--loops && host_busy); |
| 116 | |
| 117 | if (loops == 0) |
| 118 | return recover_master(smbus_base, |
| 119 | SMBUS_WAIT_UNTIL_READY_TIMEOUT); |
| 120 | |
| 121 | /* Clear any lingering errors, so the transaction will run. */ |
| 122 | outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); |
| 123 | |
| 124 | /* Set up transaction */ |
| 125 | /* Disable interrupts */ |
| 126 | outb(ctrl, (smbus_base + SMBHSTCTL)); |
| 127 | |
| 128 | /* Set the device I'm talking to. */ |
| 129 | outb(xmitadd, smbus_base + SMBXMITADD); |
| 130 | |
| 131 | return 0; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 132 | } |
| 133 | |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 134 | static int execute_command(unsigned int smbus_base) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 135 | { |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 136 | unsigned int loops = SMBUS_TIMEOUT; |
| 137 | u8 status; |
| 138 | |
| 139 | /* Start the command. */ |
| 140 | outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START), |
| 141 | smbus_base + SMBHSTCTL); |
| 142 | |
| 143 | /* Poll for it to start. */ |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 144 | do { |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 145 | smbus_delay(); |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 146 | |
| 147 | /* If we poll too slow, we could miss HOST_BUSY flag |
| 148 | * set and detect INTR or x_ERR flags instead here. |
| 149 | */ |
| 150 | status = inb(smbus_base + SMBHSTSTAT); |
| 151 | status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS); |
| 152 | } while (--loops && status == 0); |
| 153 | |
| 154 | if (loops == 0) |
| 155 | return recover_master(smbus_base, |
| 156 | SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT); |
| 157 | |
| 158 | return 0; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 159 | } |
| 160 | |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 161 | static int complete_command(unsigned int smbus_base) |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 162 | { |
| 163 | unsigned int loops = SMBUS_TIMEOUT; |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 164 | u8 status; |
| 165 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 166 | do { |
| 167 | smbus_delay(); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 168 | status = inb(smbus_base + SMBHSTSTAT); |
| 169 | } while (--loops && !host_completed(status)); |
| 170 | |
| 171 | if (loops == 0) |
| 172 | return recover_master(smbus_base, |
| 173 | SMBUS_WAIT_UNTIL_DONE_TIMEOUT); |
| 174 | |
| 175 | return cb_err_from_stat(status); |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 176 | } |
| 177 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 178 | int do_smbus_read_byte(unsigned int smbus_base, u8 device, |
| 179 | unsigned int address) |
| 180 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 181 | int ret; |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 182 | u8 byte; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 183 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 184 | /* Set up for a byte data read. */ |
| 185 | ret = setup_command(smbus_base, I801_BYTE_DATA, XMIT_READ(device)); |
| 186 | if (ret < 0) |
| 187 | return ret; |
| 188 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 189 | /* Set the command/address... */ |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 190 | outb(address, smbus_base + SMBHSTCMD); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 191 | |
| 192 | /* Clear the data byte... */ |
| 193 | outb(0, smbus_base + SMBHSTDAT0); |
| 194 | |
| 195 | /* Start the command */ |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 196 | ret = execute_command(smbus_base); |
| 197 | if (ret < 0) |
| 198 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 199 | |
| 200 | /* Poll for transaction completion */ |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 201 | ret = complete_command(smbus_base); |
| 202 | if (ret < 0) |
| 203 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 204 | |
| 205 | /* Read results of transaction */ |
| 206 | byte = inb(smbus_base + SMBHSTDAT0); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 207 | return byte; |
| 208 | } |
| 209 | |
| 210 | int do_smbus_write_byte(unsigned int smbus_base, u8 device, |
| 211 | unsigned int address, unsigned int data) |
| 212 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 213 | int ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 214 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 215 | /* Set up for a byte data write. */ |
| 216 | ret = setup_command(smbus_base, I801_BYTE_DATA, XMIT_WRITE(device)); |
| 217 | if (ret < 0) |
| 218 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 219 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 220 | /* Set the command/address... */ |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 221 | outb(address, smbus_base + SMBHSTCMD); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 222 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 223 | /* Set the data byte... */ |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 224 | outb(data, smbus_base + SMBHSTDAT0); |
| 225 | |
| 226 | /* Start the command */ |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 227 | ret = execute_command(smbus_base); |
| 228 | if (ret < 0) |
| 229 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 230 | |
| 231 | /* Poll for transaction completion */ |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 232 | return complete_command(smbus_base); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 233 | } |
| 234 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 235 | static int block_cmd_loop(unsigned int smbus_base, |
| 236 | u8 *buf, const unsigned int max_bytes, int flags) |
| 237 | { |
| 238 | u8 status; |
| 239 | unsigned int loops = SMBUS_TIMEOUT; |
| 240 | int ret, bytes = 0; |
| 241 | int is_write_cmd = flags & BLOCK_WRITE; |
| 242 | int sw_drives_nak = flags & BLOCK_I2C; |
| 243 | |
| 244 | /* Hardware limitations. */ |
| 245 | if (flags == (BLOCK_WRITE | BLOCK_I2C)) |
| 246 | return SMBUS_ERROR; |
| 247 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 248 | /* Set number of bytes to transfer. */ |
| 249 | /* Reset number of bytes to transfer so we notice later it |
| 250 | * was really updated with the transaction. */ |
| 251 | if (!sw_drives_nak) { |
| 252 | if (is_write_cmd) |
| 253 | outb(max_bytes, smbus_base + SMBHSTDAT0); |
| 254 | else |
| 255 | outb(0, smbus_base + SMBHSTDAT0); |
| 256 | } |
| 257 | |
| 258 | /* Send first byte from buffer, bytes_sent increments after |
| 259 | * hardware acknowledges it. |
| 260 | */ |
| 261 | if (is_write_cmd) |
| 262 | outb(*buf++, smbus_base + SMBBLKDAT); |
| 263 | |
| 264 | /* Start the command */ |
| 265 | ret = execute_command(smbus_base); |
| 266 | if (ret < 0) |
| 267 | return ret; |
| 268 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 269 | /* Poll for transaction completion */ |
| 270 | do { |
| 271 | status = inb(smbus_base + SMBHSTSTAT); |
| 272 | |
| 273 | if (status & SMBHSTSTS_BYTE_DONE) { /* Byte done */ |
| 274 | |
| 275 | if (is_write_cmd) { |
| 276 | bytes++; |
| 277 | if (bytes < max_bytes) |
| 278 | outb(*buf++, smbus_base + SMBBLKDAT); |
| 279 | } else { |
| 280 | if (bytes < max_bytes) |
| 281 | *buf++ = inb(smbus_base + SMBBLKDAT); |
| 282 | bytes++; |
| 283 | |
| 284 | /* Indicate that next byte is the last one. */ |
| 285 | if (sw_drives_nak && (bytes + 1 >= max_bytes)) { |
| 286 | outb(inb(smbus_base + SMBHSTCTL) |
| 287 | | SMBHSTCNT_LAST_BYTE, |
| 288 | smbus_base + SMBHSTCTL); |
| 289 | } |
| 290 | |
| 291 | } |
| 292 | |
| 293 | /* Engine internally completes the transaction |
| 294 | * and clears HOST_BUSY flag once the byte count |
| 295 | * has been reached or LAST_BYTE was set. |
| 296 | */ |
| 297 | outb(SMBHSTSTS_BYTE_DONE, smbus_base + SMBHSTSTAT); |
| 298 | } |
| 299 | |
| 300 | } while (--loops && !host_completed(status)); |
| 301 | |
| 302 | dprintk("%s: status = %02x, len = %d / %d, loops = %d\n", |
| 303 | __func__, status, bytes, max_bytes, SMBUS_TIMEOUT - loops); |
| 304 | |
| 305 | if (loops == 0) |
| 306 | return recover_master(smbus_base, |
| 307 | SMBUS_WAIT_UNTIL_DONE_TIMEOUT); |
| 308 | |
| 309 | ret = cb_err_from_stat(status); |
| 310 | if (ret < 0) |
| 311 | return ret; |
| 312 | |
| 313 | return bytes; |
| 314 | } |
| 315 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 316 | int do_smbus_block_read(unsigned int smbus_base, u8 device, u8 cmd, |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 317 | unsigned int max_bytes, u8 *buf) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 318 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 319 | int ret, slave_bytes; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 320 | |
Kyösti Mälkki | c17e855 | 2017-08-20 23:48:23 +0300 | [diff] [blame] | 321 | max_bytes = MIN(SMBUS_BLOCK_MAXLEN, max_bytes); |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 322 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 323 | /* Set up for a block data read. */ |
| 324 | ret = setup_command(smbus_base, I801_BLOCK_DATA, XMIT_READ(device)); |
| 325 | if (ret < 0) |
| 326 | return ret; |
| 327 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 328 | /* Set the command/address... */ |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 329 | outb(cmd, smbus_base + SMBHSTCMD); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 330 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 331 | /* Execute block transaction. */ |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 332 | ret = block_cmd_loop(smbus_base, buf, max_bytes, BLOCK_READ); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 333 | if (ret < 0) |
| 334 | return ret; |
| 335 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 336 | /* Post-check we received complete message. */ |
| 337 | slave_bytes = inb(smbus_base + SMBHSTDAT0); |
| 338 | if (ret < slave_bytes) |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 339 | return SMBUS_ERROR; |
| 340 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 341 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | int do_smbus_block_write(unsigned int smbus_base, u8 device, u8 cmd, |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 345 | const unsigned int bytes, const u8 *buf) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 346 | { |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 347 | int ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 348 | |
Kyösti Mälkki | c17e855 | 2017-08-20 23:48:23 +0300 | [diff] [blame] | 349 | if (bytes > SMBUS_BLOCK_MAXLEN) |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 350 | return SMBUS_ERROR; |
| 351 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 352 | /* Set up for a block data write. */ |
| 353 | ret = setup_command(smbus_base, I801_BLOCK_DATA, XMIT_WRITE(device)); |
| 354 | if (ret < 0) |
| 355 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 356 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 357 | /* Set the command/address... */ |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 358 | outb(cmd, smbus_base + SMBHSTCMD); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 359 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 360 | /* Execute block transaction. */ |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 361 | ret = block_cmd_loop(smbus_base, (u8 *)buf, bytes, BLOCK_WRITE); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 362 | if (ret < 0) |
| 363 | return ret; |
| 364 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 365 | if (ret < bytes) |
Kyösti Mälkki | c17e855 | 2017-08-20 23:48:23 +0300 | [diff] [blame] | 366 | return SMBUS_ERROR; |
| 367 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 368 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 369 | } |
| 370 | |
| 371 | /* Only since ICH5 */ |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 372 | static int has_i2c_read_command(void) |
| 373 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 374 | if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) || |
| 375 | CONFIG(SOUTHBRIDGE_INTEL_I82801DX)) |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 376 | return 0; |
| 377 | return 1; |
| 378 | } |
| 379 | |
| 380 | int do_i2c_eeprom_read(unsigned int smbus_base, u8 device, |
Kyösti Mälkki | 1e39236 | 2017-08-20 21:36:03 +0300 | [diff] [blame] | 381 | unsigned int offset, const unsigned int bytes, u8 *buf) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 382 | { |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 383 | int ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 384 | |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 385 | if (!has_i2c_read_command()) |
| 386 | return SMBUS_ERROR; |
| 387 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 388 | /* Set up for a i2c block data read. |
| 389 | * |
| 390 | * FIXME: Address parameter changes to XMIT_READ(device) with |
| 391 | * some revision of PCH. Presumably hardware revisions that |
| 392 | * do not have i2c block write support internally set LSB. |
| 393 | */ |
| 394 | ret = setup_command(smbus_base, I801_I2C_BLOCK_DATA, |
| 395 | XMIT_WRITE(device)); |
| 396 | if (ret < 0) |
| 397 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 398 | |
| 399 | /* device offset */ |
| 400 | outb(offset, smbus_base + SMBHSTDAT1); |
| 401 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 402 | /* Execute block transaction. */ |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 403 | ret = block_cmd_loop(smbus_base, buf, bytes, BLOCK_READ | BLOCK_I2C); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 404 | if (ret < 0) |
| 405 | return ret; |
| 406 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 407 | /* Post-check we received complete message. */ |
| 408 | if (ret < bytes) |
Kyösti Mälkki | 1e39236 | 2017-08-20 21:36:03 +0300 | [diff] [blame] | 409 | return SMBUS_ERROR; |
| 410 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 411 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 412 | } |
Frans Hendriks | e48be35 | 2019-06-19 11:01:27 +0200 | [diff] [blame] | 413 | |
| 414 | /* |
| 415 | * The caller is responsible of settings HOSTC I2C_EN bit prior to making this |
| 416 | * call! |
| 417 | */ |
| 418 | int do_i2c_block_write(unsigned int smbus_base, u8 device, |
| 419 | unsigned int bytes, u8 *buf) |
| 420 | { |
| 421 | u8 cmd; |
| 422 | int ret; |
| 423 | |
| 424 | if (!CONFIG(SOC_INTEL_BRASWELL)) |
| 425 | return SMBUS_ERROR; |
| 426 | |
| 427 | if (!bytes || (bytes > SMBUS_BLOCK_MAXLEN)) |
| 428 | return SMBUS_ERROR; |
| 429 | |
| 430 | /* Set up for a block data write. */ |
| 431 | ret = setup_command(smbus_base, I801_BLOCK_DATA, XMIT_WRITE(device)); |
| 432 | if (ret < 0) |
| 433 | return ret; |
| 434 | |
| 435 | /* |
| 436 | * In i2c mode SMBus controller sequence on bus will be: |
| 437 | * <SMBXINTADD> <SMBHSTDAT1> <SMBBLKDAT> .. <SMBBLKDAT> |
| 438 | * The SMBHSTCMD must be written also to ensure the SMBUs controller |
| 439 | * will generate the i2c sequence. |
| 440 | */ |
| 441 | cmd = *buf++; |
| 442 | bytes--; |
| 443 | outb(cmd, smbus_base + SMBHSTCMD); |
| 444 | outb(cmd, smbus_base + SMBHSTDAT1); |
| 445 | |
| 446 | /* Execute block transaction. */ |
| 447 | ret = block_cmd_loop(smbus_base, buf, bytes, BLOCK_WRITE); |
| 448 | if (ret < 0) |
| 449 | return ret; |
| 450 | |
| 451 | if (ret < bytes) |
| 452 | return SMBUS_ERROR; |
| 453 | |
| 454 | ret++; /* 1st byte has been written using SMBHSTDAT1 */ |
| 455 | return ret; |
| 456 | } |