Wim Vervoorn | 7c04acf | 2019-12-05 13:45:41 +0100 | [diff] [blame^] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s5_enable_ac" = "0" |
| 5 | register "deep_s5_enable_dc" = "0" |
| 6 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 7 | |
| 8 | # GPE configuration |
| 9 | # Note that GPE events called out in ASL code rely on this |
| 10 | # route. i.e. If this route changes then the affected GPE |
| 11 | # offset bits also need to be changed. |
| 12 | register "gpe0_dw0" = "GPP_C" |
| 13 | register "gpe0_dw1" = "GPP_D" |
| 14 | register "gpe0_dw2" = "GPP_E" |
| 15 | |
| 16 | # CPLD host command ranges are in 0x280-0x2BF |
| 17 | # EC PNP registers are at 0x6e and 0x6f |
| 18 | register "gen1_dec" = "0x003c0281" |
| 19 | register "gen3_dec" = "0x0004006d" |
| 20 | |
| 21 | # LPC serial IRQ |
| 22 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 23 | |
| 24 | # Enable "Intel Speed Shift Technology" |
| 25 | register "speed_shift_enable" = "1" |
| 26 | |
| 27 | # Enable DPTF |
| 28 | register "dptf_enable" = "0" |
| 29 | |
| 30 | # FSP Configuration |
| 31 | register "EnableAzalia" = "0" |
| 32 | register "SmbusEnable" = "1" |
| 33 | register "ScsEmmcEnabled" = "1" |
| 34 | register "ScsEmmcHs400Enabled" = "1" |
| 35 | register "SkipExtGfxScan" = "1" |
| 36 | register "Device4Enable" = "1" |
| 37 | register "SaGv" = "SaGv_Enabled" |
| 38 | register "SaImguEnable" = "0" |
| 39 | register "Cio2Enable" = "0" |
| 40 | register "PmTimerDisabled" = "1" |
| 41 | register "HeciEnabled" = "0" |
| 42 | register "EnableLan" = "1" |
| 43 | |
| 44 | register "EnableSata" = "1" |
| 45 | register "SataSalpSupport" = "1" |
| 46 | register "SataPortsEnable" = "{ \ |
| 47 | [0] = 1, \ |
| 48 | [1] = 0, \ |
| 49 | [2] = 0, \ |
| 50 | [3] = 0, \ |
| 51 | [4] = 0, \ |
| 52 | [5] = 0, \ |
| 53 | [6] = 0, \ |
| 54 | [7] = 0, \ |
| 55 | }" |
| 56 | |
| 57 | register "pirqa_routing" = "PCH_IRQ11" |
| 58 | register "pirqb_routing" = "PCH_IRQ10" |
| 59 | register "pirqc_routing" = "PCH_IRQ11" |
| 60 | register "pirqd_routing" = "PCH_IRQ11" |
| 61 | register "pirqe_routing" = "PCH_IRQ11" |
| 62 | register "pirqf_routing" = "PCH_IRQ11" |
| 63 | register "pirqg_routing" = "PCH_IRQ11" |
| 64 | register "pirqh_routing" = "PCH_IRQ11" |
| 65 | |
| 66 | # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 67 | # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
| 68 | register "PmConfigSlpS3MinAssert" = "2" |
| 69 | |
| 70 | # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
| 71 | register "PmConfigSlpS4MinAssert" = "4" |
| 72 | |
| 73 | # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
| 74 | register "PmConfigSlpSusMinAssert" = "3" |
| 75 | |
| 76 | # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
| 77 | register "PmConfigSlpAMinAssert" = "3" |
| 78 | |
| 79 | # VR Settings Configuration for 4 Domains |
| 80 | #+----------------+-------+-------+-------+-------+ |
| 81 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 82 | #+----------------+-------+-------+-------+-------+ |
| 83 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 84 | #| Psi2Threshold | 5A | 5A | 5A | 5A | |
| 85 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 86 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 87 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 88 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 89 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 90 | #| IccMax | 7A | 34A | 35A | 35A | |
| 91 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 92 | #+----------------+-------+-------+-------+-------+ |
| 93 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 94 | .vr_config_enable = 1, \ |
| 95 | .psi1threshold = VR_CFG_AMP(20), \ |
| 96 | .psi2threshold = VR_CFG_AMP(5), \ |
| 97 | .psi3threshold = VR_CFG_AMP(1), \ |
| 98 | .psi3enable = 1, \ |
| 99 | .psi4enable = 1, \ |
| 100 | .imon_slope = 0, \ |
| 101 | .imon_offset = 0, \ |
| 102 | .icc_max = VR_CFG_AMP(7), \ |
| 103 | .voltage_limit = 1520 \ |
| 104 | }" |
| 105 | |
| 106 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 107 | .vr_config_enable = 1, \ |
| 108 | .psi1threshold = VR_CFG_AMP(20), \ |
| 109 | .psi2threshold = VR_CFG_AMP(5), \ |
| 110 | .psi3threshold = VR_CFG_AMP(1), \ |
| 111 | .psi3enable = 1, \ |
| 112 | .psi4enable = 1, \ |
| 113 | .imon_slope = 0, \ |
| 114 | .imon_offset = 0, \ |
| 115 | .icc_max = VR_CFG_AMP(34), \ |
| 116 | .voltage_limit = 1520 \ |
| 117 | }" |
| 118 | |
| 119 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 120 | .vr_config_enable = 1, \ |
| 121 | .psi1threshold = VR_CFG_AMP(20), \ |
| 122 | .psi2threshold = VR_CFG_AMP(5), \ |
| 123 | .psi3threshold = VR_CFG_AMP(1), \ |
| 124 | .psi3enable = 1, \ |
| 125 | .psi4enable = 1, \ |
| 126 | .imon_slope = 0, \ |
| 127 | .imon_offset = 0, \ |
| 128 | .icc_max = VR_CFG_AMP(35),\ |
| 129 | .voltage_limit = 1520 \ |
| 130 | }" |
| 131 | |
| 132 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 133 | .vr_config_enable = 1, \ |
| 134 | .psi1threshold = VR_CFG_AMP(20), \ |
| 135 | .psi2threshold = VR_CFG_AMP(5), \ |
| 136 | .psi3threshold = VR_CFG_AMP(1), \ |
| 137 | .psi3enable = 1, \ |
| 138 | .psi4enable = 1, \ |
| 139 | .imon_slope = 0, \ |
| 140 | .imon_offset = 0, \ |
| 141 | .icc_max = VR_CFG_AMP(35), \ |
| 142 | .voltage_limit = 1520 \ |
| 143 | }" |
| 144 | |
| 145 | # Send an extra VR mailbox command for the PS4 exit issue |
| 146 | register "SendVrMbxCmd" = "2" |
| 147 | |
| 148 | # Enable Root ports. |
| 149 | # PCIE Port 1 disabled |
| 150 | # PCIE Port 2 disabled |
| 151 | |
| 152 | # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard |
| 153 | register "PcieRpEnable[2]" = "1" |
| 154 | # Disable CLKREQ# |
| 155 | register "PcieRpClkReqSupport[2]" = "0" |
| 156 | |
| 157 | # PCIE Port 4 disabled |
| 158 | # PCIE Port 5 x1 -> MODULE i219 |
| 159 | |
| 160 | # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard |
| 161 | register "PcieRpEnable[5]" = "1" |
| 162 | register "PcieRpClkReqSupport[5]" = "0" |
| 163 | |
| 164 | # PCIE Port 7 Disabled |
| 165 | # PCIE Port 8 Disabled |
| 166 | |
| 167 | # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA |
| 168 | register "PcieRpEnable[8]" = "1" |
| 169 | # Disable CLKREQ# |
| 170 | register "PcieRpClkReqSupport[8]" = "0" |
| 171 | # Use Hot Plug subsystem |
| 172 | register "PcieRpHotPlug[8]" = "1" |
| 173 | |
| 174 | # USB 2.0 Enable all ports |
| 175 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2 |
| 176 | register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 1 |
| 177 | register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 2 |
| 178 | register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 1 |
| 179 | register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M2 Port |
| 180 | register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disabled |
| 181 | register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # Audio board |
| 182 | register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disabled |
| 183 | register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled |
| 184 | register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled |
| 185 | register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled |
| 186 | register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled |
| 187 | |
| 188 | # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled |
| 189 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 2 |
| 190 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 1 |
| 191 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 2 |
| 192 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 1 |
| 193 | register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled |
| 194 | register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled |
| 195 | |
| 196 | register "SsicPortEnable" = "0" |
| 197 | |
| 198 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 199 | register "SerialIoDevMode" = "{ \ |
| 200 | [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ |
| 201 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ |
| 202 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| 203 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
| 204 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ |
| 205 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ |
| 206 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 207 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 208 | [PchSerialIoIndexUart0] = PchSerialIoPci, \ |
| 209 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
| 210 | [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ |
| 211 | }" |
| 212 | |
| 213 | # Lock Down |
| 214 | register "common_soc_config" = "{ |
| 215 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 216 | }" |
| 217 | |
| 218 | device cpu_cluster 0 on |
| 219 | device lapic 0 on end |
| 220 | end |
| 221 | device domain 0 on |
| 222 | device pci 00.0 on end # Host Bridge |
| 223 | device pci 02.0 on end # Integrated Graphics Device |
| 224 | device pci 04.0 on end # |
| 225 | device pci 08.0 on end # Gaussian Mixture Model |
| 226 | device pci 14.0 on end # USB xHCI |
| 227 | device pci 14.1 on end # USB xDCI (OTG) |
| 228 | device pci 14.2 on end # Thermal Subsystem |
| 229 | device pci 17.0 on end # SATA |
| 230 | device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN |
| 231 | device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 |
| 232 | device pci 1d.0 on end # PCI Express Port 9 x4 FPGA |
| 233 | device pci 1e.0 on end # UART #0 |
| 234 | device pci 1e.4 on end # eMMC |
| 235 | device pci 1e.5 off end # SDIO |
| 236 | device pci 1f.0 on # LPC Interface |
| 237 | chip drivers/pc80/tpm |
| 238 | device pnp 0c31.0 on end |
| 239 | end |
| 240 | end # LPC Bridge |
| 241 | device pci 1f.1 on end # P2SB |
| 242 | device pci 1f.2 on end # Power Management Controller |
| 243 | device pci 1f.4 on end # SMBus |
| 244 | device pci 1f.5 on end # PCH SPI |
| 245 | device pci 1f.6 on end # GbE |
| 246 | end |
| 247 | end |