Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 2 | |
Felix Held | 95f1bb8 | 2021-05-07 18:46:36 +0200 | [diff] [blame] | 3 | #include <amdblocks/alib.h> |
| 4 | |
Marc Jones | 509e5fd | 2018-08-01 12:45:03 -0600 | [diff] [blame] | 5 | External(\_SB.ALIB, MethodObj) |
| 6 | |
Martin Roth | ec23f04 | 2017-11-22 19:21:55 -0700 | [diff] [blame] | 7 | /* System Bus */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 8 | /* _SB.PCI0 */ |
| 9 | |
| 10 | /* Operating System Capabilities Method */ |
| 11 | Method(_OSC,4) |
| 12 | { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 13 | /* Check for proper PCI/PCIe UUID */ |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 14 | If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 15 | { |
| 16 | /* Let OS control everything */ |
| 17 | Return (Arg3) |
| 18 | } Else { |
Marc Jones | 1faa11e | 2018-08-15 22:17:45 -0600 | [diff] [blame] | 19 | CreateDWordField(Arg3,0,CDW1) |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 20 | CDW1 |= 4 // Unrecognized UUID |
| 21 | Return (Arg3) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 22 | } |
| 23 | } |
| 24 | |
| 25 | /* Describe the Southbridge devices */ |
| 26 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 27 | /* 0:14.0 - SMBUS */ |
| 28 | Device(SBUS) { |
| 29 | Name(_ADR, 0x00140000) |
| 30 | } /* end SBUS */ |
| 31 | |
| 32 | #include "usb.asl" |
| 33 | |
| 34 | /* 0:14.2 - I2S Audio */ |
| 35 | |
| 36 | /* 0:14.3 - LPC */ |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 37 | #include <soc/amd/common/acpi/lpc.asl> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 38 | |
| 39 | /* 0:14.7 - SD Controller */ |
| 40 | Device(SDCN) { |
| 41 | Name(_ADR, 0x00140007) |
Raul E Rangel | 29150c8 | 2019-04-23 16:02:15 -0600 | [diff] [blame] | 42 | |
| 43 | Method(_PS0) { |
| 44 | FDDC(24, 0) |
| 45 | } |
| 46 | Method(_PS3) { |
| 47 | FDDC(24, 3) |
| 48 | } |
| 49 | Method(_PSC) { |
| 50 | Return(SDTD) |
| 51 | } |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 52 | } /* end SDCN */ |
| 53 | |
| 54 | Name(CRES, ResourceTemplate() { |
| 55 | /* Set the Bus number and Secondary Bus number for the PCI0 device |
| 56 | * The Secondary bus range for PCI0 lets the system |
| 57 | * know what bus values are allowed on the downstream |
| 58 | * side of this PCI bus if there is a PCI-PCI bridge. |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 59 | * PCI buses can have 256 secondary buses which |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 60 | * range from [0-0xFF] but they do not need to be |
| 61 | * sequential. |
| 62 | */ |
| 63 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 64 | 0x0000, /* address granularity */ |
| 65 | 0x0000, /* range minimum */ |
Marshall Dawson | 6744dfe | 2017-06-14 16:09:07 -0600 | [diff] [blame] | 66 | 0x00ff, /* range maximum */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 67 | 0x0000, /* translation */ |
| 68 | 0x0100, /* length */ |
| 69 | ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ |
| 70 | |
Marshall Dawson | 6744dfe | 2017-06-14 16:09:07 -0600 | [diff] [blame] | 71 | IO(Decode16, 0x0cf8, 0x0cf8, 1, 8) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 72 | |
| 73 | WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 74 | 0x0000, /* address granularity */ |
| 75 | 0x0000, /* range minimum */ |
Marshall Dawson | 6744dfe | 2017-06-14 16:09:07 -0600 | [diff] [blame] | 76 | 0x0cf7, /* range maximum */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 77 | 0x0000, /* translation */ |
Marshall Dawson | 6744dfe | 2017-06-14 16:09:07 -0600 | [diff] [blame] | 78 | 0x0cf8 /* length */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 79 | ) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 80 | |
| 81 | WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 82 | 0x0000, /* address granularity */ |
Marshall Dawson | 6744dfe | 2017-06-14 16:09:07 -0600 | [diff] [blame] | 83 | 0x0d00, /* range minimum */ |
| 84 | 0xffff, /* range maximum */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 85 | 0x0000, /* translation */ |
Marshall Dawson | 6744dfe | 2017-06-14 16:09:07 -0600 | [diff] [blame] | 86 | 0xf300 /* length */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 87 | ) |
| 88 | |
Marshall Dawson | 6744dfe | 2017-06-14 16:09:07 -0600 | [diff] [blame] | 89 | Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ |
| 90 | Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 91 | |
| 92 | /* memory space for PCI BARs below 4GB */ |
| 93 | Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) |
| 94 | }) /* End Name(_SB.PCI0.CRES) */ |
| 95 | |
| 96 | Method(_CRS, 0) { |
| 97 | /* DBGO("\\_SB\\PCI0\\_CRS\n") */ |
| 98 | CreateDWordField(CRES, ^MMIO._BAS, MM1B) |
| 99 | CreateDWordField(CRES, ^MMIO._LEN, MM1L) |
| 100 | |
| 101 | /* |
| 102 | * Declare memory between TOM1 and 4GB as available |
| 103 | * for PCI MMIO. |
| 104 | * Use ShiftLeft to avoid 64bit constant (for XP). |
| 105 | * This will work even if the OS does 32bit arithmetic, as |
| 106 | * 32bit (0x00000000 - TOM1) will wrap and give the same |
| 107 | * result as 64bit (0x100000000 - TOM1). |
| 108 | */ |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 109 | MM1B = TOM1 |
| 110 | Local0 = 0x10000000 << 4 |
| 111 | Local0 -= TOM1 |
| 112 | MM1L = Local0 |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 113 | |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 114 | Return (CRES) /* note to change the Name buffer */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 115 | } /* end of Method(_SB.PCI0._CRS) */ |
| 116 | |
| 117 | /* |
| 118 | * |
| 119 | * FIRST METHOD CALLED UPON BOOT |
| 120 | * |
| 121 | * 1. If debugging, print current OS and ACPI interpreter. |
| 122 | * 2. Get PCI Interrupt routing from ACPI VSM, this |
| 123 | * value is based on user choice in BIOS setup. |
| 124 | */ |
Marc Jones | 509e5fd | 2018-08-01 12:45:03 -0600 | [diff] [blame] | 125 | Method(_INI, 0, Serialized) { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 126 | /* DBGO("\\_SB\\_INI\n") */ |
| 127 | /* DBGO(" DSDT.ASL code from ") */ |
| 128 | /* DBGO(__DATE__) */ |
| 129 | /* DBGO(" ") */ |
| 130 | /* DBGO(__TIME__) */ |
| 131 | /* DBGO("\n Sleep states supported: ") */ |
| 132 | /* DBGO("\n") */ |
| 133 | /* DBGO(" \\_OS=") */ |
| 134 | /* DBGO(\_OS) */ |
| 135 | /* DBGO("\n \\_REV=") */ |
| 136 | /* DBGO(\_REV) */ |
| 137 | /* DBGO("\n") */ |
| 138 | |
Marc Jones | 509e5fd | 2018-08-01 12:45:03 -0600 | [diff] [blame] | 139 | /* Send ALIB Function 1 the AC/DC state */ |
| 140 | Name(F1BF, Buffer(0x03){}) |
| 141 | CreateWordField(F1BF, 0, F1SZ) |
| 142 | CreateByteField(F1BF, 2, F1DA) |
| 143 | |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 144 | F1SZ = 3 |
| 145 | F1DA= \PWRS |
Marc Jones | 509e5fd | 2018-08-01 12:45:03 -0600 | [diff] [blame] | 146 | |
Felix Held | 95f1bb8 | 2021-05-07 18:46:36 +0200 | [diff] [blame] | 147 | \_SB.ALIB(ALIB_FUNCTION_REPORT_AC_DC_STATE, F1BF) |
Marc Jones | 509e5fd | 2018-08-01 12:45:03 -0600 | [diff] [blame] | 148 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 149 | } /* End Method(_SB._INI) */ |
| 150 | |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 151 | OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000) |
| 152 | Field( SMIC, ByteAcc, NoLock, Preserve) { |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 153 | /* MISC registers */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 154 | offset (0x03ee), |
| 155 | U3PS, 2, /* Usb3PowerSel */ |
| 156 | |
| 157 | offset (0x0e28), |
| 158 | ,29 , |
| 159 | SARP, 1, /* Sata Ref Clock Powerdown */ |
| 160 | U2RP, 1, /* Usb2 Ref Clock Powerdown */ |
| 161 | U3RP, 1, /* Usb3 Ref Clock Powerdown */ |
| 162 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 163 | /* XHCI_PM registers */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 164 | offset (0x1c00), |
| 165 | , 1, |
| 166 | ,6, |
| 167 | U3PY, 1, |
| 168 | , 7, |
| 169 | UD3P, 1, /* bit 15 */ |
| 170 | U3PR, 1, /* bit 16 */ |
| 171 | , 11, |
| 172 | FWLM, 1, /* FirmWare Load Mode */ |
| 173 | FPLS, 1, /* Fw PreLoad Start */ |
| 174 | FPLC, 1, /* Fw PreLoad Complete */ |
| 175 | |
| 176 | offset (0x1c04), |
| 177 | UA04, 16, |
| 178 | , 15, |
| 179 | ROAM, 1, /* 1= ROM 0=RAM */ |
| 180 | |
| 181 | offset (0x1c08), |
| 182 | UA08, 32, |
| 183 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 184 | /* AOAC Registers */ |
| 185 | offset (0x1e4a), /* I2C0 D3 Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 186 | I0TD, 2, |
| 187 | , 1, |
| 188 | I0PD, 1, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 189 | offset (0x1e4b), /* I2C0 D3 State */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 190 | I0DS, 3, |
| 191 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 192 | offset (0x1e4c), /* I2C1 D3 Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 193 | I1TD, 2, |
| 194 | , 1, |
| 195 | I1PD, 1, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 196 | offset (0x1e4d), /* I2C1 D3 State */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 197 | I1DS, 3, |
| 198 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 199 | offset (0x1e4e), /* I2C2 D3 Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 200 | I2TD, 2, |
| 201 | , 1, |
| 202 | I2PD, 1, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 203 | offset (0x1e4f), /* I2C2 D3 State */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 204 | I2DS, 3, |
| 205 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 206 | offset (0x1e50), /* I2C3 D3 Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 207 | I3TD, 2, |
| 208 | , 1, |
| 209 | I3PD, 1, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 210 | offset (0x1e51), /* I2C3 D3 State */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 211 | I3DS, 3, |
| 212 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 213 | offset (0x1e56), /* UART0 D3 Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 214 | U0TD, 2, |
| 215 | , 1, |
| 216 | U0PD, 1, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 217 | offset (0x1e57), /* UART0 D3 State */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 218 | U0DS, 3, |
| 219 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 220 | offset (0x1e58), /* UART1 D3 Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 221 | U1TD, 2, |
| 222 | , 1, |
| 223 | U1PD, 1, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 224 | offset (0x1e59), /* UART1 D3 State */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 225 | U1DS, 3, |
| 226 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 227 | offset (0x1e5e), /* SATA D3 Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 228 | SATD, 2, |
| 229 | , 1, |
| 230 | SAPD, 1, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 231 | offset (0x1e5f), /* SATA D3 State */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 232 | SADS, 3, |
| 233 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 234 | offset (0x1e64), /* USB2 D3 Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 235 | U2TD, 2, |
| 236 | , 1, |
| 237 | U2PD, 1, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 238 | offset (0x1e65), /* USB2 D3 State */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 239 | U2DS, 3, |
| 240 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 241 | offset (0x1e6e), /* USB3 D3 Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 242 | U3TD, 2, |
| 243 | , 1, |
| 244 | U3PD, 1, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 245 | offset (0x1e6f), /* USB3 D3 State */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 246 | U3DS, 3, |
| 247 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 248 | offset (0x1e70), /* SD D3 Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 249 | SDTD, 2, |
| 250 | , 1, |
Raul E Rangel | 29150c8 | 2019-04-23 16:02:15 -0600 | [diff] [blame] | 251 | SDPD, 1, |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 252 | , 1, |
Raul E Rangel | 29150c8 | 2019-04-23 16:02:15 -0600 | [diff] [blame] | 253 | , 1, |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 254 | SDRT, 1, |
| 255 | SDSC, 1, |
| 256 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 257 | offset (0x1e71), /* SD D3 State */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 258 | SDDS, 3, |
| 259 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 260 | offset (0x1e80), /* Shadow Register Request */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 261 | , 15, |
| 262 | RQ15, 1, |
| 263 | , 2, |
| 264 | RQ18, 1, |
| 265 | , 4, |
| 266 | RQ23, 1, |
| 267 | RQ24, 1, |
| 268 | , 5, |
| 269 | RQTY, 1, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 270 | offset (0x1e84), /* Shadow Register Status */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 271 | , 15, |
| 272 | SASR, 1, /* SATA 15 Shadow Reg Request Status Register */ |
| 273 | , 2, |
| 274 | U2SR, 1, /* USB2 18 Shadow Reg Request Status Register */ |
| 275 | , 4, |
| 276 | U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */ |
| 277 | SDSR, 1, /* SD 24 Shadow Reg Request Status Register */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 278 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 279 | offset (0x1ea0), /* PwrGood Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 280 | PG1A, 1, |
| 281 | PG2_, 1, |
| 282 | ,1, |
| 283 | U3PG, 1, /* Usb3 Power Good BIT3 */ |
| 284 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 285 | offset (0x1ea3), /* PwrGood Control b[31:24] */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 286 | PGA3, 8 , |
| 287 | } |
| 288 | |
Kyösti Mälkki | c0733e1 | 2021-02-14 06:58:39 +0200 | [diff] [blame] | 289 | Field(PCFG, DwordAcc, NoLock, Preserve) |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 290 | { |
| 291 | /* XHCI */ |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 292 | Offset(0x00080010), /* Base address */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 293 | XHBA, 32, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 294 | Offset(0x0008002c), /* Subsystem ID / Vendor ID */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 295 | XH2C, 32, |
| 296 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 297 | Offset(0x00080048), /* Indirect PCI Index Register */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 298 | IDEX, 32, |
| 299 | DATA, 32, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 300 | Offset(0x00080054), /* PME Control / Status */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 301 | U_PS, 2, |
| 302 | |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 303 | /* EHCI */ |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 304 | Offset(0x00090004), /* Control */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 305 | , 1, |
| 306 | EHME, 1, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 307 | Offset(0x00090010), /* Base address */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 308 | EHBA, 32, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 309 | Offset(0x0009002c), /* Subsystem ID / Vendor ID */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 310 | EH2C, 32, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 311 | Offset(0x00090054), /* EHCI Spare 1 */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 312 | EH54, 8, |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 313 | Offset(0x00090064), /* Misc Control 2 */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 314 | EH64, 8, |
| 315 | |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 316 | Offset(0x000900c4), /* PME Control / Status */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 317 | E_PS, 2, |
| 318 | |
| 319 | /* LPC Bridge */ |
Marshall Dawson | 5fdd201 | 2018-10-01 14:57:02 -0600 | [diff] [blame] | 320 | Offset(0x000a30cb), /* ClientRomProtect[31:24] */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 321 | , 7, |
| 322 | AUSS, 1, /* AutoSizeStart */ |
Marshall Dawson | b77c76c | 2018-09-26 16:19:36 -0600 | [diff] [blame] | 323 | } |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 324 | |
| 325 | /* |
| 326 | * Arg0:device: |
| 327 | * 5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1, |
| 328 | * 15=SATA, 18=EHCI, 23=xHCI, 24=SD |
| 329 | * Arg1:D-state |
| 330 | */ |
| 331 | Mutex (FDAS, 0) /* FCH Device AOAC Semophore */ |
| 332 | Method(FDDC, 2, Serialized) |
| 333 | { |
| 334 | Acquire(FDAS, 0xffff) |
| 335 | |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 336 | if (Arg1 == 0) { |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 337 | Switch(ToInteger(Arg0)) { |
| 338 | Case(Package() {5, 15, 24}) { |
Felix Singer | 7b8ac00 | 2022-12-26 08:45:56 +0100 | [diff] [blame^] | 339 | PG1A = 1 |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 340 | } |
| 341 | Case(Package() {6, 7, 8, 11, 12, 18}) { |
Felix Singer | 7b8ac00 | 2022-12-26 08:45:56 +0100 | [diff] [blame^] | 342 | PG2_ = 1 |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 343 | } |
| 344 | } |
| 345 | /* put device into D0 */ |
| 346 | Switch(ToInteger(Arg0)) |
| 347 | { |
| 348 | Case(5) { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 349 | I0TD = 0x00 |
Felix Singer | 7b8ac00 | 2022-12-26 08:45:56 +0100 | [diff] [blame^] | 350 | I0PD = 1 |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 351 | Local0 = I0DS |
| 352 | while(Local0 != 0x7) { |
| 353 | Local0 = I0DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 354 | } |
| 355 | } |
| 356 | Case(6) { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 357 | I1TD = 0x00 |
Felix Singer | 7b8ac00 | 2022-12-26 08:45:56 +0100 | [diff] [blame^] | 358 | I1PD = 1 |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 359 | Local0 = I1DS |
| 360 | while(Local0 != 0x7) { |
| 361 | Local0 = I1DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 362 | } |
| 363 | } |
| 364 | Case(7) { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 365 | I2TD = 0x00 |
Felix Singer | 7b8ac00 | 2022-12-26 08:45:56 +0100 | [diff] [blame^] | 366 | I2PD = 1 |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 367 | Local0 = I2DS |
| 368 | while(Local0 != 0x7) { |
| 369 | Local0 = I2DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 370 | } |
| 371 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 372 | Case(8) { |
| 373 | I3TD = 0x00 |
Felix Singer | 7b8ac00 | 2022-12-26 08:45:56 +0100 | [diff] [blame^] | 374 | I3PD = 1 |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 375 | Local0 = I3DS |
| 376 | while(Local0 != 0x7) { |
| 377 | Local0 = I3DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 378 | } |
| 379 | } |
| 380 | Case(11) { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 381 | U0TD = 0x00 |
Felix Singer | 7b8ac00 | 2022-12-26 08:45:56 +0100 | [diff] [blame^] | 382 | U0PD = 1 |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 383 | Local0 = U0DS |
| 384 | while(Local0 != 0x7) { |
| 385 | Local0 = U0DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 386 | } |
| 387 | } |
| 388 | Case(12) { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 389 | U1TD = 0x00 |
Felix Singer | 7b8ac00 | 2022-12-26 08:45:56 +0100 | [diff] [blame^] | 390 | U1PD = 1 |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 391 | Local0 = U1DS |
| 392 | while(Local0 != 0x7) { |
| 393 | Local0 = U1DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 394 | } |
| 395 | } |
| 396 | /* todo Case(15) { STD0()} */ /* SATA */ |
Marshall Dawson | fdb846d | 2018-09-26 15:43:21 -0600 | [diff] [blame] | 397 | Case(18) { U2D0()} /* EHCI */ |
| 398 | Case(23) { U3D0()} /* XHCI */ |
Raul E Rangel | 29150c8 | 2019-04-23 16:02:15 -0600 | [diff] [blame] | 399 | Case(24) { /* SD */ |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 400 | SDTD = 0x00 |
Felix Singer | 7b8ac00 | 2022-12-26 08:45:56 +0100 | [diff] [blame^] | 401 | SDPD = 1 |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 402 | Local0 = SDDS |
| 403 | while(Local0 != 0x7) { |
| 404 | Local0 = SDDS |
Raul E Rangel | 29150c8 | 2019-04-23 16:02:15 -0600 | [diff] [blame] | 405 | } |
| 406 | } |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 407 | } |
| 408 | } else { |
| 409 | /* put device into D3cold */ |
| 410 | Switch(ToInteger(Arg0)) |
| 411 | { |
| 412 | Case(5) { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 413 | I0PD = Zero |
| 414 | Local0 = I0DS |
| 415 | while(Local0 != 0x0) { |
| 416 | Local0 = I0DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 417 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 418 | I0TD = 0x03 |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 419 | } |
| 420 | Case(6) { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 421 | I1PD = Zero |
| 422 | Local0 = I1DS |
| 423 | while(Local0 != 0x0) { |
| 424 | Local0 = I1DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 425 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 426 | I1TD = 0x03 |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 427 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 428 | Case(7) { |
| 429 | I2PD = Zero |
| 430 | Local0 = I2DS |
| 431 | while(Local0 != 0x0) { |
| 432 | Local0 = I2DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 433 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 434 | I2TD = 0x03 |
| 435 | } |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 436 | Case(8) { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 437 | I3PD = Zero |
| 438 | Local0 = I3DS |
| 439 | while(Local0 != 0x0) { |
| 440 | Local0 = I3DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 441 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 442 | I3TD = 0x03 |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 443 | } |
| 444 | Case(11) { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 445 | U0PD = Zero |
| 446 | Local0 = U0DS |
| 447 | while(Local0 != 0x0) { |
| 448 | Local0 = U0DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 449 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 450 | U0TD = 0x03 |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 451 | } |
| 452 | Case(12) { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 453 | U1PD = Zero |
| 454 | Local0 = U1DS |
| 455 | while(Local0 != 0x0) { |
| 456 | Local0 = U1DS |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 457 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 458 | U1TD = 0x03 |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 459 | } |
| 460 | /* todo Case(15) { STD3()} */ /* SATA */ |
Marshall Dawson | fdb846d | 2018-09-26 15:43:21 -0600 | [diff] [blame] | 461 | Case(18) { U2D3()} /* EHCI */ |
| 462 | Case(23) { U3D3()} /* XHCI */ |
Raul E Rangel | 29150c8 | 2019-04-23 16:02:15 -0600 | [diff] [blame] | 463 | Case(24) { /* SD */ |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 464 | SDPD = Zero |
| 465 | Local0 = SDDS |
| 466 | while(Local0 != 0x0) { |
| 467 | Local0 = SDDS |
Raul E Rangel | 29150c8 | 2019-04-23 16:02:15 -0600 | [diff] [blame] | 468 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 469 | SDTD = 0x03 |
Raul E Rangel | 29150c8 | 2019-04-23 16:02:15 -0600 | [diff] [blame] | 470 | } |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 471 | } |
| 472 | /* Turn off Power */ |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 473 | if (I0TD == 3) { |
| 474 | if (SATD == 3) { |
| 475 | if (SDTD == 3) { PG1A = Zero } |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 476 | } |
| 477 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 478 | if (I1TD == 3) { |
| 479 | if (I2TD == 3) { |
| 480 | if (I3TD == 3) { |
| 481 | if (U0TD == 3) { |
| 482 | if (U1TD == 3) { |
| 483 | if (U2TD == 3) { |
| 484 | PG2_ = Zero |
Marshall Dawson | 14331fd | 2018-09-26 16:12:56 -0600 | [diff] [blame] | 485 | } |
| 486 | } |
| 487 | } |
| 488 | } |
| 489 | } |
| 490 | } |
| 491 | } |
| 492 | Release(FDAS) |
| 493 | } |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 494 | |
| 495 | Method(FPTS,0, Serialized) /* FCH _PTS */ |
| 496 | { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 497 | if (\XHCE == one) { |
| 498 | if (U3TD != 0x03) { |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 499 | FDDC(23, 3) |
| 500 | } |
| 501 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 502 | if (U2TD != 0x03) { |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 503 | FDDC(18, 3) |
| 504 | } |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 505 | } |
| 506 | |
| 507 | Method(FWAK,0, Serialized) /* FCH _WAK */ |
| 508 | { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 509 | if (\XHCE == one) { |
| 510 | if (U3TD == 0x03) { |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 511 | FDDC(23, 0) |
| 512 | } |
| 513 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 514 | if (U2TD == 0x03) { |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 515 | FDDC(18, 0) |
| 516 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 517 | if (\UT0E == zero) { |
| 518 | if (U0TD != 0x03) { |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 519 | FDDC(11, 3) |
| 520 | } |
| 521 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 522 | if (\UT1E == zero) { |
| 523 | if (U1TD != 0x03) { |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 524 | FDDC(12, 3) |
| 525 | } |
| 526 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 527 | if (\IC0E == zero) { |
| 528 | if (I0TD != 0x03) { |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 529 | FDDC(5, 3) |
| 530 | } |
| 531 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 532 | if (\IC1E == zero) { |
| 533 | if (I1TD != 0x03) { |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 534 | FDDC(6, 3) |
| 535 | } |
| 536 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 537 | if (\IC2E == zero) { |
| 538 | if (I2TD != 0x03) { |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 539 | FDDC(7, 3) |
| 540 | } |
| 541 | } |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 542 | if (\IC3E == zero) { |
| 543 | if (I3TD != 0x03) { |
Marshall Dawson | 9c5dc1f | 2018-09-26 16:07:59 -0600 | [diff] [blame] | 544 | FDDC(8, 3) |
| 545 | } |
| 546 | } |
| 547 | } |
Marshall Dawson | cb2b70b | 2018-09-26 15:52:00 -0600 | [diff] [blame] | 548 | |
| 549 | /* |
| 550 | * Helper for setting a bit in AOACxA0 PwrGood Control |
| 551 | * Arg0: bit to set or clear |
| 552 | * Arg1: 0 = clear bit[Arg0], non-zero = set bit[Arg0] |
| 553 | */ |
| 554 | Method(PWGC,2, Serialized) |
| 555 | { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 556 | Local0 = PGA3 & 0xdf /* do SwUsb3SlpShutdown below */ |
| 557 | if (Arg1) { |
| 558 | Local0 |= Arg0 |
Marshall Dawson | cb2b70b | 2018-09-26 15:52:00 -0600 | [diff] [blame] | 559 | } else { |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 560 | Local1 = ~Arg0 |
| 561 | Local0 &= Local1 |
Marshall Dawson | cb2b70b | 2018-09-26 15:52:00 -0600 | [diff] [blame] | 562 | } |
Elyes HAOUAS | 72ff4b7 | 2021-02-05 20:06:25 +0100 | [diff] [blame] | 563 | PGA3 = Local0 |
Elyes HAOUAS | 8684643 | 2020-09-24 15:47:34 +0200 | [diff] [blame] | 564 | if (Arg0 == 0x20) { /* if SwUsb3SlpShutdown */ |
| 565 | Local0 = PGA3 |
| 566 | Local0 &= Arg0 |
| 567 | while(!Local0) { /* wait SwUsb3SlpShutdown to complete */ |
| 568 | Local0 = PGA3 |
| 569 | Local0 &= Arg0 |
Marshall Dawson | cb2b70b | 2018-09-26 15:52:00 -0600 | [diff] [blame] | 570 | } |
| 571 | } |
| 572 | } |