| Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | /* |
| 4 | * e7505.h: PCI configuration space for the Intel E7501 memory controller |
| 5 | */ |
| 6 | |
| 7 | #ifndef NORTHBRIDGE_INTEL_E7505_E7505_H |
| 8 | #define NORTHBRIDGE_INTEL_E7505_E7505_H |
| 9 | |
| 10 | /************ D0:F0 ************/ |
| 11 | // Register offsets |
| 12 | #define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */ |
| 13 | #define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */ |
| 14 | |
| 15 | #define PAM_0 0x59 |
| 16 | |
| 17 | #define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */ |
| 18 | #define DRB_ROW_1 0x61 |
| 19 | #define DRB_ROW_2 0x62 |
| 20 | #define DRB_ROW_3 0x63 |
| 21 | #define DRB_ROW_4 0x64 |
| 22 | #define DRB_ROW_5 0x65 |
| 23 | #define DRB_ROW_6 0x66 |
| 24 | #define DRB_ROW_7 0x67 |
| 25 | |
| 26 | #define DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */ |
| 27 | #define DRT 0x78 /* DRAM Timing register, 32 bit */ |
| 28 | #define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ |
| 29 | #define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ |
| 30 | #define CKDIS 0x8C /* Clock disable register, 8 bit */ |
| 31 | #define SMRAMC 0x9D |
| 32 | #define ESMRAMC 0x9E |
| 33 | #define APSIZE 0xB4 |
| 34 | #define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ |
| 35 | #define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ |
| 36 | #define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */ |
| 37 | #define SKPD 0xDE /* Scratchpad register, 16 bit */ |
| 38 | #define DVNP 0xE0 /* Device Not Present, 16 bit */ |
| 39 | #define MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */ |
| 40 | |
| 41 | // CAS# Latency bits in the DRAM Timing (DRT) register |
| 42 | #define DRT_CAS_2_5 (0<<4) |
| 43 | #define DRT_CAS_2_0 (1<<4) |
| 44 | #define DRT_CAS_MASK (3<<4) |
| 45 | |
| 46 | // Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register |
| 47 | #define RAM_COMMAND_NOP (1<<4) |
| 48 | #define RAM_COMMAND_PRECHARGE (2<<4) |
| 49 | #define RAM_COMMAND_MRS (3<<4) |
| 50 | #define RAM_COMMAND_EMRS (4<<4) |
| 51 | #define RAM_COMMAND_CBR (6<<4) |
| 52 | #define RAM_COMMAND_NORMAL (7<<4) |
| 53 | |
| 54 | #define DRC_DONE (1 << 29) |
| 55 | |
| 56 | // RCOMP Memory Map offsets |
| 57 | // Conjecture based on apparent similarity between E7501 and 855PM |
| 58 | // Intel doc. 252613-003 describes these for 855PM |
| 59 | |
| 60 | #define SMRCTL 0x20 /* System Memory RCOMP Control Register? */ |
| 61 | #define DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */ |
| 62 | #define CKESTR 0x31 /* Strength control for CKE signal group? */ |
| 63 | #define CSBSTR 0x32 /* Strength control for CS# signal group? */ |
| 64 | #define CKSTR 0x33 /* Strength control for CK signal group? */ |
| 65 | #define RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */ |
| 66 | |
| 67 | /************ D0:F1 ************/ |
| 68 | // Register offsets |
| 69 | #define FERR_GLOBAL 0x40 /* First global error register, 32 bits */ |
| 70 | #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ |
| 71 | #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ |
| 72 | #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ |
| 73 | |
| 74 | /************ D1:F0 ************/ |
| 75 | |
| 76 | #define APSIZE1 0x74 |
| 77 | |
| 78 | #endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */ |