| Tobias Diedrich | 7a95204 | 2017-12-03 10:09:28 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; version 2 of |
| 11 | * the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 21 | #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) |
| 22 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 23 | #else |
| 24 | #include <northbridge/intel/sandybridge/raminit.h> |
| 25 | #endif |
| 26 | |
| 27 | #if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) |
| 28 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
| 29 | { |
| 30 | struct pei_data pei_data_template = { |
| 31 | .pei_version = PEI_VERSION, |
| 32 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 33 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
| 34 | .epbar = DEFAULT_EPBAR, |
| 35 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 36 | .smbusbar = SMBUS_IO_BASE, |
| 37 | .wdbbar = 0x4000000, |
| 38 | .wdbsize = 0x1000, |
| 39 | .hpet_address = CONFIG_HPET_ADDRESS, |
| 40 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
| 41 | .pmbase = DEFAULT_PMBASE, |
| 42 | .gpiobase = DEFAULT_GPIOBASE, |
| 43 | .thermalbase = 0xfed08000, |
| 44 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 45 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 46 | .spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 }, |
| 47 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 48 | .ec_present = 0, |
| 49 | .gbe_enable = 1, |
| 50 | // 0 = leave channel enabled |
| 51 | // 1 = disable dimm 0 on channel |
| 52 | // 2 = disable dimm 1 on channel |
| 53 | // 3 = disable dimm 0+1 on channel |
| 54 | .dimm_channel0_disabled = 2, |
| 55 | .dimm_channel1_disabled = 2, |
| 56 | .max_ddr3_freq = 1333, |
| 57 | .usb_port_config = { |
| 58 | #define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current } |
| 59 | #include "usb.h" |
| 60 | }, |
| 61 | }; |
| 62 | *pei_data = pei_data_template; |
| 63 | } |
| 64 | |
| 65 | int mainboard_should_reset_usb(int s3resume) |
| 66 | { |
| 67 | return !s3resume; |
| 68 | } |
| 69 | #endif |