Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 7a87c9203e8d79a76293a0cf2821e9401730dc1e / . / src / northbridge / intel / ironlake / quickpath.c
blob: 90e62e236f955cd481179ad98be1b18421e25bea [file] [log] [blame]
Angel Pons7a87c922021-01-15 22:50:41 +0100[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <console/console.h>
4#include <delay.h>
5#include <device/pci_def.h>
6#include <device/pci_ops.h>
7#include <northbridge/intel/ironlake/raminit.h>
8#include <types.h>
9
10#define NORTHBRIDGE PCI_DEV(0, 0, 0)
11
12static unsigned int gcd(unsigned int a, unsigned int b)
13{
14 unsigned int t;
15 if (a > b) {
16 t = a;
17 a = b;
18 b = t;
19 }
20 /* invariant a < b. */
21 while (a) {
22 t = b % a;
23 b = a;
24 a = t;
25 }
26 return b;
27}
28
29static inline int div_roundup(int a, int b)
30{
31 return DIV_ROUND_UP(a, b);
32}
33
34static unsigned int lcm(unsigned int a, unsigned int b)
35{
36 return (a * b) / gcd(a, b);
37}
38
39struct stru1 {
40 u8 freqs_reversed;
41 u8 freq_diff_reduced;
42 u8 freq_min_reduced;
43 u8 divisor_f4_to_fmax;
44 u8 divisor_f3_to_fmax;
45 u8 freq4_to_max_remainder;
46 u8 freq3_to_2_remainder;
47 u8 freq3_to_2_remaindera;
48 u8 freq4_to_2_remainder;
49 int divisor_f3_to_f1, divisor_f4_to_f2;
50 int common_time_unit_ps;
51 int freq_max_reduced;
52};
53
54static void
55compute_frequence_ratios(struct raminfo *info, u16 freq1, u16 freq2,
56 int num_cycles_2, int num_cycles_1, int round_it,
57 int add_freqs, struct stru1 *result)
58{
59 int g;
60 int common_time_unit_ps;
61 int freq1_reduced, freq2_reduced;
62 int freq_min_reduced;
63 int freq_max_reduced;
64 int freq3, freq4;
65
66 g = gcd(freq1, freq2);
67 freq1_reduced = freq1 / g;
68 freq2_reduced = freq2 / g;
69 freq_min_reduced = MIN(freq1_reduced, freq2_reduced);
70 freq_max_reduced = MAX(freq1_reduced, freq2_reduced);
71
72 common_time_unit_ps = div_roundup(900000, lcm(freq1, freq2));
73 freq3 = div_roundup(num_cycles_2, common_time_unit_ps) - 1;
74 freq4 = div_roundup(num_cycles_1, common_time_unit_ps) - 1;
75 if (add_freqs) {
76 freq3 += freq2_reduced;
77 freq4 += freq1_reduced;
78 }
79
80 if (round_it) {
81 result->freq3_to_2_remainder = 0;
82 result->freq3_to_2_remaindera = 0;
83 result->freq4_to_max_remainder = 0;
84 result->divisor_f4_to_f2 = 0;
85 result->divisor_f3_to_f1 = 0;
86 } else {
87 if (freq2_reduced < freq1_reduced) {
88 result->freq3_to_2_remainder =
89 result->freq3_to_2_remaindera =
90 freq3 % freq1_reduced - freq1_reduced + 1;
91 result->freq4_to_max_remainder =
92 -(freq4 % freq1_reduced);
93 result->divisor_f3_to_f1 = freq3 / freq1_reduced;
94 result->divisor_f4_to_f2 =
95 (freq4 -
96 (freq1_reduced - freq2_reduced)) / freq2_reduced;
97 result->freq4_to_2_remainder =
98 -(char)((freq1_reduced - freq2_reduced) +
99 ((u8) freq4 -
100 (freq1_reduced -
101 freq2_reduced)) % (u8) freq2_reduced);
102 } else {
103 if (freq2_reduced > freq1_reduced) {
104 result->freq4_to_max_remainder =
105 (freq4 % freq2_reduced) - freq2_reduced + 1;
106 result->freq4_to_2_remainder =
107 freq4 % freq_max_reduced -
108 freq_max_reduced + 1;
109 } else {
110 result->freq4_to_max_remainder =
111 -(freq4 % freq2_reduced);
112 result->freq4_to_2_remainder =
113 -(char)(freq4 % freq_max_reduced);
114 }
115 result->divisor_f4_to_f2 = freq4 / freq2_reduced;
116 result->divisor_f3_to_f1 =
117 (freq3 -
118 (freq2_reduced - freq1_reduced)) / freq1_reduced;
119 result->freq3_to_2_remainder = -(freq3 % freq2_reduced);
120 result->freq3_to_2_remaindera =
121 -(char)((freq_max_reduced - freq_min_reduced) +
122 (freq3 -
123 (freq_max_reduced -
124 freq_min_reduced)) % freq1_reduced);
125 }
126 }
127 result->divisor_f3_to_fmax = freq3 / freq_max_reduced;
128 result->divisor_f4_to_fmax = freq4 / freq_max_reduced;
129 if (round_it) {
130 if (freq2_reduced > freq1_reduced) {
131 if (freq3 % freq_max_reduced)
132 result->divisor_f3_to_fmax++;
133 }
134 if (freq2_reduced < freq1_reduced) {
135 if (freq4 % freq_max_reduced)
136 result->divisor_f4_to_fmax++;
137 }
138 }
139 result->freqs_reversed = (freq2_reduced < freq1_reduced);
140 result->freq_diff_reduced = freq_max_reduced - freq_min_reduced;
141 result->freq_min_reduced = freq_min_reduced;
142 result->common_time_unit_ps = common_time_unit_ps;
143 result->freq_max_reduced = freq_max_reduced;
144}
145
146static void set_274265(struct raminfo *info)
147{
148 int delay_a_ps, delay_b_ps, delay_c_ps, delay_d_ps;
149 int delay_e_ps, delay_e_cycles, delay_f_cycles;
150 int delay_e_over_cycle_ps;
151 int cycletime_ps;
152 int channel;
153
154 delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info);
155 info->training.reg2ca9_bit0 = 0;
156 for (channel = 0; channel < NUM_CHANNELS; channel++) {
157 cycletime_ps =
158 900000 / lcm(2 * info->fsb_frequency, frequency_11(info));
159 delay_d_ps =
160 (halfcycle_ps(info) * get_max_timing(info, channel) >> 6)
161 - info->some_delay_3_ps_rounded + 200;
162 if (!
163 ((info->silicon_revision == 0
164 || info->silicon_revision == 1)
165 && (info->revision >= 8)))
166 delay_d_ps += halfcycle_ps(info) * 2;
167 delay_d_ps +=
168 halfcycle_ps(info) * (!info->revision_flag_1 +
169 info->some_delay_2_halfcycles_ceil +
170 2 * info->some_delay_1_cycle_floor +
171 info->clock_speed_index +
172 2 * info->cas_latency - 7 + 11);
173 delay_d_ps += info->revision >= 8 ? 2758 : 4428;
174
175 MCHBAR32_AND_OR(0x140, 0xfaffffff, 0x2000000);
176 MCHBAR32_AND_OR(0x138, 0xfaffffff, 0x2000000);
177 if ((MCHBAR8(0x144) & 0x1f) > 0x13)
178 delay_d_ps += 650;
179 delay_c_ps = delay_d_ps + 1800;
180 if (delay_c_ps <= delay_a_ps)
181 delay_e_ps = 0;
182 else
183 delay_e_ps =
184 cycletime_ps * div_roundup(delay_c_ps - delay_a_ps,
185 cycletime_ps);
186
187 delay_e_over_cycle_ps = delay_e_ps % (2 * halfcycle_ps(info));
188 delay_e_cycles = delay_e_ps / (2 * halfcycle_ps(info));
189 delay_f_cycles =
190 div_roundup(2500 - delay_e_over_cycle_ps,
191 2 * halfcycle_ps(info));
192 if (delay_f_cycles > delay_e_cycles) {
193 info->delay46_ps[channel] = delay_e_ps;
194 delay_e_cycles = 0;
195 } else {
196 info->delay46_ps[channel] =
197 delay_e_over_cycle_ps +
198 2 * halfcycle_ps(info) * delay_f_cycles;
199 delay_e_cycles -= delay_f_cycles;
200 }
201
202 if (info->delay46_ps[channel] < 2500) {
203 info->delay46_ps[channel] = 2500;
204 info->training.reg2ca9_bit0 = 1;
205 }
206 delay_b_ps = halfcycle_ps(info) + delay_c_ps;
207 if (delay_b_ps <= delay_a_ps)
208 delay_b_ps = 0;
209 else
210 delay_b_ps -= delay_a_ps;
211 info->delay54_ps[channel] =
212 cycletime_ps * div_roundup(delay_b_ps,
213 cycletime_ps) -
214 2 * halfcycle_ps(info) * delay_e_cycles;
215 if (info->delay54_ps[channel] < 2500)
216 info->delay54_ps[channel] = 2500;
217 info->training.reg274265[channel][0] = delay_e_cycles;
218 if (delay_d_ps + 7 * halfcycle_ps(info) <=
219 24 * halfcycle_ps(info))
220 info->training.reg274265[channel][1] = 0;
221 else
222 info->training.reg274265[channel][1] =
223 div_roundup(delay_d_ps + 7 * halfcycle_ps(info),
224 4 * halfcycle_ps(info)) - 6;
225 MCHBAR32((channel << 10) + 0x274) =
226 info->training.reg274265[channel][1] |
227 (info->training.reg274265[channel][0] << 16);
228 info->training.reg274265[channel][2] =
229 div_roundup(delay_c_ps + 3 * fsbcycle_ps(info),
230 4 * halfcycle_ps(info)) + 1;
231 MCHBAR16((channel << 10) + 0x265) =
232 info->training.reg274265[channel][2] << 8;
233 }
234 if (info->training.reg2ca9_bit0)
235 MCHBAR8_OR(0x2ca9, 1);
236 else
237 MCHBAR8_AND(0x2ca9, ~1);
238}
239
240static void restore_274265(struct raminfo *info)
241{
242 int channel;
243
244 for (channel = 0; channel < NUM_CHANNELS; channel++) {
245 MCHBAR32((channel << 10) + 0x274) =
246 (info->cached_training->reg274265[channel][0] << 16) |
247 info->cached_training->reg274265[channel][1];
248 MCHBAR16((channel << 10) + 0x265) =
249 info->cached_training->reg274265[channel][2] << 8;
250 }
251 if (info->cached_training->reg2ca9_bit0)
252 MCHBAR8_OR(0x2ca9, 1);
253 else
254 MCHBAR8_AND(0x2ca9, ~1);
255}
256
257static void
258set_2d5x_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
259 int num_cycles_2, int num_cycles_1, int num_cycles_3,
260 int num_cycles_4, int reverse)
261{
262 struct stru1 vv;
263 char multiplier;
264
265 compute_frequence_ratios(info, freq1, freq2, num_cycles_2, num_cycles_1,
266 0, 1, &vv);
267
268 multiplier =
269 div_roundup(MAX
270 (div_roundup(num_cycles_2, vv.common_time_unit_ps) +
271 div_roundup(num_cycles_3, vv.common_time_unit_ps),
272 div_roundup(num_cycles_1,
273 vv.common_time_unit_ps) +
274 div_roundup(num_cycles_4, vv.common_time_unit_ps))
275 + vv.freq_min_reduced - 1, vv.freq_max_reduced) - 1;
276
277 u32 y =
278 (u8) ((vv.freq_max_reduced - vv.freq_min_reduced) +
279 vv.freq_max_reduced * multiplier)
280 | (vv.
281 freqs_reversed << 8) | ((u8) (vv.freq_min_reduced *
282 multiplier) << 16) | ((u8) (vv.
283 freq_min_reduced
284 *
285 multiplier)
286 << 24);
287 u32 x =
288 vv.freq3_to_2_remaindera | (vv.freq4_to_2_remainder << 8) | (vv.
289 divisor_f3_to_f1
290 << 16)
291 | (vv.divisor_f4_to_f2 << 20) | (vv.freq_min_reduced << 24);
292 if (reverse) {
293 MCHBAR32(reg) = y;
294 MCHBAR32(reg + 4) = x;
295 } else {
296 MCHBAR32(reg + 4) = y;
297 MCHBAR32(reg) = x;
298 }
299}
300
301static void
302set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
303 int num_cycles_1, int num_cycles_2, int num_cycles_3,
304 int num_cycles_4)
305{
306 struct stru1 ratios1;
307 struct stru1 ratios2;
308
309 compute_frequence_ratios(info, freq1, freq2, num_cycles_1, num_cycles_2,
310 0, 1, &ratios2);
311 compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4,
312 0, 1, &ratios1);
313 printk(RAM_SPEW, "[%x] <= %x\n", reg,
314 ratios1.freq4_to_max_remainder | (ratios2.
315 freq4_to_max_remainder
316 << 8)
317 | (ratios1.divisor_f4_to_fmax << 16) | (ratios2.
318 divisor_f4_to_fmax
319 << 20));
320 MCHBAR32(reg) = ratios1.freq4_to_max_remainder |
321 (ratios2.freq4_to_max_remainder << 8) |
322 (ratios1.divisor_f4_to_fmax << 16) |
323 (ratios2.divisor_f4_to_fmax << 20);
324}
325
326static void
327set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2,
328 int num_cycles_2, int num_cycles_1, int round_it, int add_freqs)
329{
330 struct stru1 ratios;
331
332 compute_frequence_ratios(info, freq1, freq2, num_cycles_2, num_cycles_1,
333 round_it, add_freqs, &ratios);
334 switch (mode) {
335 case 0:
336 MCHBAR32(reg + 4) = ratios.freq_diff_reduced |
337 (ratios.freqs_reversed << 8);
338 MCHBAR32(reg) = ratios.freq3_to_2_remainder |
339 (ratios.freq4_to_max_remainder << 8) |
340 (ratios.divisor_f3_to_fmax << 16) |
341 (ratios.divisor_f4_to_fmax << 20) |
342 (ratios.freq_min_reduced << 24);
343 break;
344
345 case 1:
346 MCHBAR32(reg) = ratios.freq3_to_2_remainder |
347 (ratios.divisor_f3_to_fmax << 16);
348 break;
349
350 case 2:
351 MCHBAR32(reg) = ratios.freq3_to_2_remainder |
352 (ratios.freq4_to_max_remainder << 8) |
353 (ratios.divisor_f3_to_fmax << 16) |
354 (ratios.divisor_f4_to_fmax << 20);
355 break;
356
357 case 4:
358 MCHBAR32(reg) = (ratios.divisor_f3_to_fmax << 4) |
359 (ratios.divisor_f4_to_fmax << 8) |
360 (ratios.freqs_reversed << 12) |
361 (ratios.freq_min_reduced << 16) |
362 (ratios.freq_diff_reduced << 24);
363 break;
364 }
365}
366
367static void set_2dxx_series(struct raminfo *info, int s3resume)
368{
369 set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005,
370 0, 1);
371 set_2dx8_reg(info, 0x2d08, 0, 0x78, 0x78, 3273, 5033, 1, 1);
372 set_2dx8_reg(info, 0x2d10, 0, 0x78, info->fsb_frequency, 1475, 1131, 0,
373 1);
374 set_2dx8_reg(info, 0x2d18, 0, 2 * info->fsb_frequency,
375 frequency_11(info), 1231, 1524, 0, 1);
376 set_2dx8_reg(info, 0x2d20, 0, 2 * info->fsb_frequency,
377 frequency_11(info) / 2, 1278, 2008, 0, 1);
378 set_2dx8_reg(info, 0x2d28, 0, info->fsb_frequency, frequency_11(info),
379 1167, 1539, 0, 1);
380 set_2dx8_reg(info, 0x2d30, 0, info->fsb_frequency,
381 frequency_11(info) / 2, 1403, 1318, 0, 1);
382 set_2dx8_reg(info, 0x2d38, 0, info->fsb_frequency, 0x78, 3460, 5363, 1,
383 1);
384 set_2dx8_reg(info, 0x2d40, 0, info->fsb_frequency, 0x3c, 2792, 5178, 1,
385 1);
386 set_2dx8_reg(info, 0x2d48, 0, 2 * info->fsb_frequency, 0x78, 2738, 4610,
387 1, 1);
388 set_2dx8_reg(info, 0x2d50, 0, info->fsb_frequency, 0x78, 2819, 5932, 1,
389 1);
390 set_2dx8_reg(info, 0x6d4, 1, info->fsb_frequency,
391 frequency_11(info) / 2, 4000, 0, 0, 0);
392 set_2dx8_reg(info, 0x6d8, 2, info->fsb_frequency,
393 frequency_11(info) / 2, 4000, 4000, 0, 0);
394
395 if (s3resume) {
396 printk(RAM_SPEW, "[6dc] <= %x\n",
397 info->cached_training->reg_6dc);
398 MCHBAR32(0x6dc) = info->cached_training->reg_6dc;
399 } else
400 set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0,
401 info->delay46_ps[0], 0,
402 info->delay54_ps[0]);
403 set_2dx8_reg(info, 0x6e0, 1, 2 * info->fsb_frequency,
404 frequency_11(info), 2500, 0, 0, 0);
405 set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency,
406 frequency_11(info) / 2, 3500, 0, 0, 0);
407 if (s3resume) {
408 printk(RAM_SPEW, "[6e8] <= %x\n",
409 info->cached_training->reg_6e8);
410 MCHBAR32(0x6e8) = info->cached_training->reg_6e8;
411 } else
412 set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0,
413 info->delay46_ps[1], 0,
414 info->delay54_ps[1]);
415 set_2d5x_reg(info, 0x2d58, 0x78, 0x78, 864, 1195, 762, 786, 0);
416 set_2d5x_reg(info, 0x2d60, 0x195, info->fsb_frequency, 1352, 725, 455,
417 470, 0);
418 set_2d5x_reg(info, 0x2d68, 0x195, 0x3c, 2707, 5632, 3277, 2207, 0);
419 set_2d5x_reg(info, 0x2d70, 0x195, frequency_11(info) / 2, 1276, 758,
420 454, 459, 0);
421 set_2d5x_reg(info, 0x2d78, 0x195, 0x78, 1021, 799, 510, 513, 0);
422 set_2d5x_reg(info, 0x2d80, info->fsb_frequency, 0xe1, 0, 2862, 2579,
423 2588, 0);
424 set_2d5x_reg(info, 0x2d88, info->fsb_frequency, 0xe1, 0, 2690, 2405,
425 2405, 0);
426 set_2d5x_reg(info, 0x2da0, 0x78, 0xe1, 0, 2560, 2264, 2251, 0);
427 set_2d5x_reg(info, 0x2da8, 0x195, frequency_11(info), 1060, 775, 484,
428 480, 0);
429 set_2d5x_reg(info, 0x2db0, 0x195, 0x78, 4183, 6023, 2217, 2048, 0);
430 MCHBAR32(0x2dbc) = ((frequency_11(info) / 2) - 1) | 0xe00000;
431 MCHBAR32(0x2db8) = ((info->fsb_frequency - 1) << 16) | 0x77;
432}
433
434void late_quickpath_init(struct raminfo *info, const int s3resume)
435{
436 const u16 deven = pci_read_config16(NORTHBRIDGE, DEVEN);
437
438 int i, j;
439 if (s3resume && info->cached_training) {
440 restore_274265(info);
441 printk(RAM_SPEW, "reg2ca9_bit0 = %x\n",
442 info->cached_training->reg2ca9_bit0);
443 for (i = 0; i < 2; i++)
444 for (j = 0; j < 3; j++)
445 printk(RAM_SPEW, "reg274265[%d][%d] = %x\n",
446 i, j, info->cached_training->reg274265[i][j]);
447 } else {
448 set_274265(info);
449 printk(RAM_SPEW, "reg2ca9_bit0 = %x\n",
450 info->training.reg2ca9_bit0);
451 for (i = 0; i < 2; i++)
452 for (j = 0; j < 3; j++)
453 printk(RAM_SPEW, "reg274265[%d][%d] = %x\n",
454 i, j, info->training.reg274265[i][j]);
455 }
456
457 set_2dxx_series(info, s3resume);
458
459 if (!(deven & 8)) {
460 MCHBAR32_AND_OR(0x2cb0, 0, 0x40);
461 }
462
463 udelay(1000);
464
465 if (deven & 8) {
466 MCHBAR32_OR(0xff8, 0x1800);
467 MCHBAR32_AND(0x2cb0, 0x00);
468 pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
469 pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
470 pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e);
471
472 MCHBAR8(0x1150);
473 MCHBAR8(0x1151);
474 MCHBAR8(0x1022);
475 MCHBAR8(0x16d0);
476 MCHBAR32(0x1300) = 0x60606060;
477 MCHBAR32(0x1304) = 0x60606060;
478 MCHBAR32(0x1308) = 0x78797a7b;
479 MCHBAR32(0x130c) = 0x7c7d7e7f;
480 MCHBAR32(0x1310) = 0x60606060;
481 MCHBAR32(0x1314) = 0x60606060;
482 MCHBAR32(0x1318) = 0x60606060;
483 MCHBAR32(0x131c) = 0x60606060;
484 MCHBAR32(0x1320) = 0x50515253;
485 MCHBAR32(0x1324) = 0x54555657;
486 MCHBAR32(0x1328) = 0x58595a5b;
487 MCHBAR32(0x132c) = 0x5c5d5e5f;
488 MCHBAR32(0x1330) = 0x40414243;
489 MCHBAR32(0x1334) = 0x44454647;
490 MCHBAR32(0x1338) = 0x48494a4b;
491 MCHBAR32(0x133c) = 0x4c4d4e4f;
492 MCHBAR32(0x1340) = 0x30313233;
493 MCHBAR32(0x1344) = 0x34353637;
494 MCHBAR32(0x1348) = 0x38393a3b;
495 MCHBAR32(0x134c) = 0x3c3d3e3f;
496 MCHBAR32(0x1350) = 0x20212223;
497 MCHBAR32(0x1354) = 0x24252627;
498 MCHBAR32(0x1358) = 0x28292a2b;
499 MCHBAR32(0x135c) = 0x2c2d2e2f;
500 MCHBAR32(0x1360) = 0x10111213;
501 MCHBAR32(0x1364) = 0x14151617;
502 MCHBAR32(0x1368) = 0x18191a1b;
503 MCHBAR32(0x136c) = 0x1c1d1e1f;
504 MCHBAR32(0x1370) = 0x10203;
505 MCHBAR32(0x1374) = 0x4050607;
506 MCHBAR32(0x1378) = 0x8090a0b;
507 MCHBAR32(0x137c) = 0xc0d0e0f;
508 MCHBAR8(0x11cc) = 0x4e;
509 MCHBAR32(0x1110) = 0x73970404;
510 MCHBAR32(0x1114) = 0x72960404;
511 MCHBAR32(0x1118) = 0x6f950404;
512 MCHBAR32(0x111c) = 0x6d940404;
513 MCHBAR32(0x1120) = 0x6a930404;
514 MCHBAR32(0x1124) = 0x68a41404;
515 MCHBAR32(0x1128) = 0x66a21404;
516 MCHBAR32(0x112c) = 0x63a01404;
517 MCHBAR32(0x1130) = 0x609e1404;
518 MCHBAR32(0x1134) = 0x5f9c1404;
519 MCHBAR32(0x1138) = 0x5c961404;
520 MCHBAR32(0x113c) = 0x58a02404;
521 MCHBAR32(0x1140) = 0x54942404;
522 MCHBAR32(0x1190) = 0x900080a;
523 MCHBAR16(0x11c0) = 0xc40b;
524 MCHBAR16(0x11c2) = 0x303;
525 MCHBAR16(0x11c4) = 0x301;
526 MCHBAR32_AND_OR(0x1190, 0, 0x8900080a);
527 MCHBAR32(0x11b8) = 0x70c3000;
528 MCHBAR8(0x11ec) = 0xa;
529 MCHBAR16(0x1100) = 0x800;
530 MCHBAR32_AND_OR(0x11bc, 0, 0x1e84800);
531 MCHBAR16(0x11ca) = 0xfa;
532 MCHBAR32(0x11e4) = 0x4e20;
533 MCHBAR8(0x11bc) = 0xf;
534 MCHBAR16(0x11da) = 0x19;
535 MCHBAR16(0x11ba) = 0x470c;
536 MCHBAR32(0x1680) = 0xe6ffe4ff;
537 MCHBAR32(0x1684) = 0xdeffdaff;
538 MCHBAR32(0x1688) = 0xd4ffd0ff;
539 MCHBAR32(0x168c) = 0xccffc6ff;
540 MCHBAR32(0x1690) = 0xc0ffbeff;
541 MCHBAR32(0x1694) = 0xb8ffb0ff;
542 MCHBAR32(0x1698) = 0xa8ff0000;
543 MCHBAR32(0x169c) = 0xc00;
544 MCHBAR32(0x1290) = 0x5000000;
545 }
546
547 MCHBAR32(0x124c) = 0x15040d00;
548 MCHBAR32(0x1250) = 0x7f0000;
549 MCHBAR32(0x1254) = 0x1e220004;
550 MCHBAR32(0x1258) = 0x4000004;
551 MCHBAR32(0x1278) = 0x0;
552 MCHBAR32(0x125c) = 0x0;
553 MCHBAR32(0x1260) = 0x0;
554 MCHBAR32(0x1264) = 0x0;
555 MCHBAR32(0x1268) = 0x0;
556 MCHBAR32(0x126c) = 0x0;
557 MCHBAR32(0x1270) = 0x0;
558 MCHBAR32(0x1274) = 0x0;
559
560 if (deven & 8) {
561 MCHBAR16(0x1214) = 0x320;
562 MCHBAR32(0x1600) = 0x40000000;
563 MCHBAR32_AND_OR(0x11f4, 0, 0x10000000);
564 MCHBAR16_AND_OR(0x1230, 0, 0x8000);
565 MCHBAR32(0x1400) = 0x13040020;
566 MCHBAR32(0x1404) = 0xe090120;
567 MCHBAR32(0x1408) = 0x5120220;
568 MCHBAR32(0x140c) = 0x5120330;
569 MCHBAR32(0x1410) = 0xe090220;
570 MCHBAR32(0x1414) = 0x1010001;
571 MCHBAR32(0x1418) = 0x1110000;
572 MCHBAR32(0x141c) = 0x9020020;
573 MCHBAR32(0x1420) = 0xd090220;
574 MCHBAR32(0x1424) = 0x2090220;
575 MCHBAR32(0x1428) = 0x2090330;
576 MCHBAR32(0x142c) = 0xd090220;
577 MCHBAR32(0x1430) = 0x1010001;
578 MCHBAR32(0x1434) = 0x1110000;
579 MCHBAR32(0x1438) = 0x11040020;
580 MCHBAR32(0x143c) = 0x4030220;
581 MCHBAR32(0x1440) = 0x1060220;
582 MCHBAR32(0x1444) = 0x1060330;
583 MCHBAR32(0x1448) = 0x4030220;
584 MCHBAR32(0x144c) = 0x1010001;
585 MCHBAR32(0x1450) = 0x1110000;
586 MCHBAR32(0x1454) = 0x4010020;
587 MCHBAR32(0x1458) = 0xb090220;
588 MCHBAR32(0x145c) = 0x1090220;
589 MCHBAR32(0x1460) = 0x1090330;
590 MCHBAR32(0x1464) = 0xb090220;
591 MCHBAR32(0x1468) = 0x1010001;
592 MCHBAR32(0x146c) = 0x1110000;
593 MCHBAR32(0x1470) = 0xf040020;
594 MCHBAR32(0x1474) = 0xa090220;
595 MCHBAR32(0x1478) = 0x1120220;
596 MCHBAR32(0x147c) = 0x1120330;
597 MCHBAR32(0x1480) = 0xa090220;
598 MCHBAR32(0x1484) = 0x1010001;
599 MCHBAR32(0x1488) = 0x1110000;
600 MCHBAR32(0x148c) = 0x7020020;
601 MCHBAR32(0x1490) = 0x1010220;
602 MCHBAR32(0x1494) = 0x10210;
603 MCHBAR32(0x1498) = 0x10320;
604 MCHBAR32(0x149c) = 0x1010220;
605 MCHBAR32(0x14a0) = 0x1010001;
606 MCHBAR32(0x14a4) = 0x1110000;
607 MCHBAR32(0x14a8) = 0xd040020;
608 MCHBAR32(0x14ac) = 0x8090220;
609 MCHBAR32(0x14b0) = 0x1111310;
610 MCHBAR32(0x14b4) = 0x1111420;
611 MCHBAR32(0x14b8) = 0x8090220;
612 MCHBAR32(0x14bc) = 0x1010001;
613 MCHBAR32(0x14c0) = 0x1110000;
614 MCHBAR32(0x14c4) = 0x3010020;
615 MCHBAR32(0x14c8) = 0x7090220;
616 MCHBAR32(0x14cc) = 0x1081310;
617 MCHBAR32(0x14d0) = 0x1081420;
618 MCHBAR32(0x14d4) = 0x7090220;
619 MCHBAR32(0x14d8) = 0x1010001;
620 MCHBAR32(0x14dc) = 0x1110000;
621 MCHBAR32(0x14e0) = 0xb040020;
622 MCHBAR32(0x14e4) = 0x2030220;
623 MCHBAR32(0x14e8) = 0x1051310;
624 MCHBAR32(0x14ec) = 0x1051420;
625 MCHBAR32(0x14f0) = 0x2030220;
626 MCHBAR32(0x14f4) = 0x1010001;
627 MCHBAR32(0x14f8) = 0x1110000;
628 MCHBAR32(0x14fc) = 0x5020020;
629 MCHBAR32(0x1500) = 0x5090220;
630 MCHBAR32(0x1504) = 0x2071310;
631 MCHBAR32(0x1508) = 0x2071420;
632 MCHBAR32(0x150c) = 0x5090220;
633 MCHBAR32(0x1510) = 0x1010001;
634 MCHBAR32(0x1514) = 0x1110000;
635 MCHBAR32(0x1518) = 0x7040120;
636 MCHBAR32(0x151c) = 0x2090220;
637 MCHBAR32(0x1520) = 0x70b1210;
638 MCHBAR32(0x1524) = 0x70b1310;
639 MCHBAR32(0x1528) = 0x2090220;
640 MCHBAR32(0x152c) = 0x1010001;
641 MCHBAR32(0x1530) = 0x1110000;
642 MCHBAR32(0x1534) = 0x1010110;
643 MCHBAR32(0x1538) = 0x1081310;
644 MCHBAR32(0x153c) = 0x5041200;
645 MCHBAR32(0x1540) = 0x5041310;
646 MCHBAR32(0x1544) = 0x1081310;
647 MCHBAR32(0x1548) = 0x1010001;
648 MCHBAR32(0x154c) = 0x1110000;
649 MCHBAR32(0x1550) = 0x1040120;
650 MCHBAR32(0x1554) = 0x4051210;
651 MCHBAR32(0x1558) = 0xd051200;
652 MCHBAR32(0x155c) = 0xd051200;
653 MCHBAR32(0x1560) = 0x4051210;
654 MCHBAR32(0x1564) = 0x1010001;
655 MCHBAR32(0x1568) = 0x1110000;
656 MCHBAR16(0x1222) = 0x220a;
657 MCHBAR16(0x123c) = 0x1fc0;
658 MCHBAR16(0x1220) = 0x1388;
659 }
660}