Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Elyes HAOUAS | d2b9ec1 | 2018-10-27 09:41:02 +0200 | [diff] [blame] | 2 | |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 3 | #include <bootblock_common.h> |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 4 | #include <cpu/x86/pae.h> |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 5 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 7 | #include <intelblocks/cpulib.h> |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame] | 8 | #include <intelblocks/fast_spi.h> |
Kyösti Mälkki | b7908d2 | 2019-08-18 06:01:41 +0300 | [diff] [blame] | 9 | #include <intelblocks/lpc_lib.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 10 | #include <intelblocks/p2sb.h> |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 11 | #include <intelblocks/pcr.h> |
Subrata Banik | 8bf69d3 | 2017-03-09 13:43:54 +0530 | [diff] [blame] | 12 | #include <intelblocks/rtc.h> |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame] | 13 | #include <intelblocks/systemagent.h> |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 14 | #include <intelblocks/pmclib.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 15 | #include <intelblocks/tco.h> |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 16 | #include <intelblocks/uart.h> |
Andrey Petrov | f87275f | 2016-03-29 14:19:53 -0700 | [diff] [blame] | 17 | #include <soc/iomap.h> |
Andrey Petrov | 32d3995 | 2016-02-12 13:26:57 -0800 | [diff] [blame] | 18 | #include <soc/cpu.h> |
Andrey Petrov | 4520c5e | 2016-04-18 13:36:19 -0700 | [diff] [blame] | 19 | #include <soc/gpio.h> |
Sean Rhodes | 2d58d5c | 2022-01-19 08:13:38 +0000 | [diff] [blame] | 20 | #include <soc/soc_chip.h> |
Subrata Banik | 7952e28 | 2017-03-14 18:26:27 +0530 | [diff] [blame] | 21 | #include <soc/systemagent.h> |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 22 | #include <soc/pci_devs.h> |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 23 | #include <soc/pm.h> |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 24 | #include <spi-generic.h> |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 25 | |
Andrey Petrov | 4520c5e | 2016-04-18 13:36:19 -0700 | [diff] [blame] | 26 | static const struct pad_config tpm_spi_configs[] = { |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 27 | #if CONFIG(SOC_INTEL_GEMINILAKE) |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 28 | PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ |
| 29 | #else |
Andrey Petrov | 4520c5e | 2016-04-18 13:36:19 -0700 | [diff] [blame] | 30 | PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 31 | #endif |
Andrey Petrov | 4520c5e | 2016-04-18 13:36:19 -0700 | [diff] [blame] | 32 | }; |
| 33 | |
| 34 | static void tpm_enable(void) |
| 35 | { |
| 36 | /* Configure gpios */ |
| 37 | gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs)); |
| 38 | } |
| 39 | |
Lee Leahy | 2d154e8 | 2017-03-09 10:38:09 -0800 | [diff] [blame] | 40 | asmlinkage void bootblock_c_entry(uint64_t base_timestamp) |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 41 | { |
Elyes HAOUAS | c8a649c | 2018-06-10 23:36:44 +0200 | [diff] [blame] | 42 | pci_devfn_t dev; |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 43 | |
Subrata Banik | 7952e28 | 2017-03-14 18:26:27 +0530 | [diff] [blame] | 44 | bootblock_systemagent_early_init(); |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 45 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 46 | p2sb_enable_bar(); |
| 47 | p2sb_configure_hpet(); |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 48 | |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 49 | /* Decode the ACPI I/O port range for early firmware verification.*/ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 50 | dev = PCH_DEV_PMC; |
Barnali Sarkar | 9e55ff6 | 2017-06-05 20:01:14 +0530 | [diff] [blame] | 51 | pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS); |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 52 | pci_write_config16(dev, PCI_COMMAND, |
| 53 | PCI_COMMAND_IO | PCI_COMMAND_MASTER); |
| 54 | |
Subrata Banik | 8bf69d3 | 2017-03-09 13:43:54 +0530 | [diff] [blame] | 55 | enable_rtc_upper_bank(); |
Furquan Shaikh | 8d66bee | 2016-07-30 18:06:23 -0700 | [diff] [blame] | 56 | |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 57 | /* Call lib/bootblock.c main */ |
Kyösti Mälkki | 101ef0b | 2019-08-18 06:58:42 +0300 | [diff] [blame] | 58 | bootblock_main_with_basetime(base_timestamp); |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 59 | } |
Andrey Petrov | 32d3995 | 2016-02-12 13:26:57 -0800 | [diff] [blame] | 60 | |
Andrey Petrov | 33fd66b | 2016-06-22 18:58:14 -0700 | [diff] [blame] | 61 | static void enable_pmcbar(void) |
| 62 | { |
Elyes HAOUAS | c8a649c | 2018-06-10 23:36:44 +0200 | [diff] [blame] | 63 | pci_devfn_t pmc = PCH_DEV_PMC; |
Andrey Petrov | 33fd66b | 2016-06-22 18:58:14 -0700 | [diff] [blame] | 64 | |
| 65 | /* Set PMC base addresses and enable decoding. */ |
Subrata Banik | 480e7e5 | 2022-02-01 19:01:36 +0530 | [diff] [blame] | 66 | pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS); |
Andrey Petrov | 33fd66b | 2016-06-22 18:58:14 -0700 | [diff] [blame] | 67 | pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ |
| 68 | pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); |
| 69 | pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ |
Barnali Sarkar | 9e55ff6 | 2017-06-05 20:01:14 +0530 | [diff] [blame] | 70 | pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS); |
Andrey Petrov | 33fd66b | 2016-06-22 18:58:14 -0700 | [diff] [blame] | 71 | pci_write_config16(pmc, PCI_COMMAND, |
| 72 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 73 | PCI_COMMAND_MASTER); |
| 74 | } |
| 75 | |
Aaron Durbin | 672be9a | 2016-02-24 19:02:58 -0600 | [diff] [blame] | 76 | void bootblock_soc_early_init(void) |
| 77 | { |
Andrey Petrov | 33fd66b | 2016-06-22 18:58:14 -0700 | [diff] [blame] | 78 | enable_pmcbar(); |
| 79 | |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 80 | /* Clear global reset promotion bit */ |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 81 | pmc_global_reset_enable(0); |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 82 | |
Aaron Durbin | 672be9a | 2016-02-24 19:02:58 -0600 | [diff] [blame] | 83 | /* Prepare UART for serial console. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 84 | if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 85 | uart_bootblock_init(); |
Sean Rhodes | 2d58d5c | 2022-01-19 08:13:38 +0000 | [diff] [blame] | 86 | |
| 87 | uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | |
| 88 | LPC_IOE_EC_62_66; |
| 89 | |
| 90 | const config_t *config = config_of_soc(); |
| 91 | |
| 92 | |
| 93 | if (config->lpc_ioe) { |
| 94 | io_enables = config->lpc_ioe & 0x3f0f; |
| 95 | lpc_set_fixed_io_ranges(config->lpc_iod, 0x1377); |
| 96 | } else { |
| 97 | /* IO Decode Range */ |
| 98 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 99 | lpc_io_setup_comm_a_b(); |
| 100 | } |
| 101 | |
| 102 | /* IO Decode Enable */ |
| 103 | lpc_enable_fixed_io_ranges(io_enables); |
Andrey Petrov | 4520c5e | 2016-04-18 13:36:19 -0700 | [diff] [blame] | 104 | |
Sean Rhodes | 7a82a80 | 2022-06-02 11:28:43 +0100 | [diff] [blame^] | 105 | /* Program generic IO Decode Range */ |
| 106 | pch_enable_lpc(); |
| 107 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 108 | if (CONFIG(TPM_ON_FAST_SPI)) |
Andrey Petrov | 4520c5e | 2016-04-18 13:36:19 -0700 | [diff] [blame] | 109 | tpm_enable(); |
Andrey Petrov | e976bd4 | 2016-02-05 11:27:44 -0800 | [diff] [blame] | 110 | |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 111 | enable_pm_timer_emulation(); |
Andrey Petrov | f87275f | 2016-03-29 14:19:53 -0700 | [diff] [blame] | 112 | |
Bora Guvendik | 7fe9e8e | 2018-06-13 14:46:10 -0700 | [diff] [blame] | 113 | fast_spi_early_init(SPI_BASE_ADDRESS); |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 114 | |
Aaron Durbin | 5391e55 | 2017-06-02 12:16:04 -0500 | [diff] [blame] | 115 | fast_spi_cache_bios_region(); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 116 | |
| 117 | /* Initialize GPE for use as interrupt status */ |
| 118 | pmc_gpe_init(); |
Vadim Bendebury | 0d0408a | 2017-11-20 16:18:45 -0800 | [diff] [blame] | 119 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 120 | /* Program TCO Timer Halt */ |
| 121 | tco_configure(); |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 122 | |
| 123 | /* Use Nx and paging to prevent the frontend from writing back dirty |
| 124 | * cache-as-ram lines to backing store that doesn't exist when the L1I |
| 125 | * speculatively fetches a line that is sitting in the L1D. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 126 | if (CONFIG(PAGING_IN_CACHE_AS_RAM)) { |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 127 | paging_set_nxe(1); |
| 128 | paging_set_default_pat(); |
| 129 | paging_enable_for_car("pdpt", "pt"); |
| 130 | } |
Aaron Durbin | 672be9a | 2016-02-24 19:02:58 -0600 | [diff] [blame] | 131 | } |