Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Tim Chu | e27e1c1 | 2022-10-19 06:24:21 +0000 | [diff] [blame] | 3 | #include <arch/io.h> |
Marc Jones | 352ca5b | 2021-03-18 17:01:06 -0600 | [diff] [blame] | 4 | #include <console/console.h> |
Tim Chu | e27e1c1 | 2022-10-19 06:24:21 +0000 | [diff] [blame] | 5 | #include <console/uart.h> |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 6 | #include <cpu/x86/smm.h> |
Marc Jones | 352ca5b | 2021-03-18 17:01:06 -0600 | [diff] [blame] | 7 | #include <device/pci.h> |
Patrick Rudolph | 7a593ab | 2024-01-25 15:15:00 +0100 | [diff] [blame^] | 8 | #include <device/pci_ids.h> |
Tim Chu | e27e1c1 | 2022-10-19 06:24:21 +0000 | [diff] [blame] | 9 | #include <drivers/uart/uart8250reg.h> |
Marc Jones | 352ca5b | 2021-03-18 17:01:06 -0600 | [diff] [blame] | 10 | #include <intelblocks/smihandler.h> |
| 11 | #include <soc/pci_devs.h> |
| 12 | #include <soc/pm.h> |
| 13 | |
Tim Chu | e27e1c1 | 2022-10-19 06:24:21 +0000 | [diff] [blame] | 14 | struct uart8250_state { |
| 15 | uint8_t IER, IIR, MCR, LCR, DLL, DLM; |
| 16 | }; |
| 17 | |
| 18 | static struct uart8250_state s_uart8250_state; |
| 19 | |
| 20 | static void uart8250_store(unsigned int base_port) |
| 21 | { |
| 22 | /* Save previous state for restoring later. */ |
| 23 | s_uart8250_state.IER = inb(base_port + UART8250_IER); |
| 24 | s_uart8250_state.IIR = inb(base_port + UART8250_FCR); |
| 25 | s_uart8250_state.MCR = inb(base_port + UART8250_MCR); |
| 26 | s_uart8250_state.LCR = inb(base_port + UART8250_LCR); |
| 27 | s_uart8250_state.DLL = inb(base_port + UART8250_DLL); |
| 28 | s_uart8250_state.DLM = inb(base_port + UART8250_DLM); |
| 29 | } |
| 30 | |
| 31 | void smm_soc_early_init(void) |
| 32 | { |
| 33 | if (CONFIG(DRIVERS_UART_8250IO) && CONFIG(DEBUG_SMI)) |
| 34 | uart8250_store(uart_platform_base(CONFIG_UART_FOR_CONSOLE)); |
| 35 | } |
| 36 | |
| 37 | static void uart8250_restore(unsigned int base_port) |
| 38 | { |
| 39 | outb(s_uart8250_state.DLL, base_port + UART8250_DLL); |
| 40 | outb(s_uart8250_state.DLM, base_port + UART8250_DLM); |
| 41 | outb(s_uart8250_state.MCR, base_port + UART8250_MCR); |
| 42 | outb(s_uart8250_state.LCR, base_port + UART8250_LCR); |
| 43 | if ((s_uart8250_state.IIR & UART8250_IIR_FIFO_EN) == UART8250_IIR_FIFO_EN) |
| 44 | outb(UART8250_FCR_FIFO_EN, base_port + UART8250_FCR); |
| 45 | outb(s_uart8250_state.IER, base_port + UART8250_IER); |
| 46 | } |
| 47 | |
| 48 | void smm_soc_exit(void) |
| 49 | { |
| 50 | if (CONFIG(DRIVERS_UART_8250IO) && CONFIG(DEBUG_SMI)) |
| 51 | uart8250_restore(uart_platform_base(CONFIG_UART_FOR_CONSOLE)); |
| 52 | } |
| 53 | |
Marc Jones | 352ca5b | 2021-03-18 17:01:06 -0600 | [diff] [blame] | 54 | /* |
| 55 | * Specific SOC SMI handler during ramstage finalize phase |
| 56 | */ |
| 57 | void smihandler_soc_at_finalize(void) |
| 58 | { |
Patrick Rudolph | 7a593ab | 2024-01-25 15:15:00 +0100 | [diff] [blame^] | 59 | const volatile struct smm_pci_resource_info *res_store; |
| 60 | size_t res_count, found = 0; |
Tim Chu | 3ba1621 | 2022-12-14 11:27:52 +0000 | [diff] [blame] | 61 | u32 val; |
Patrick Rudolph | 7a593ab | 2024-01-25 15:15:00 +0100 | [diff] [blame^] | 62 | |
| 63 | /* SMM_FEATURE_CONTROL can only be written within SMM. */ |
| 64 | smm_pci_get_stored_resources(&res_store, &res_count); |
| 65 | for (size_t i_slot = 0; i_slot < res_count; i_slot++) { |
| 66 | if (res_store[i_slot].vendor_id != PCI_VID_INTEL || |
| 67 | res_store[i_slot].device_id != UBOX_DFX_DEVID) { |
| 68 | continue; |
| 69 | } |
| 70 | |
| 71 | val = pci_s_read_config32(res_store[i_slot].pci_addr, SMM_FEATURE_CONTROL); |
| 72 | val |= (SMM_CODE_CHK_EN | SMM_FEATURE_CONTROL_LOCK); |
| 73 | pci_s_write_config32(res_store[i_slot].pci_addr, SMM_FEATURE_CONTROL, val); |
| 74 | found ++; |
| 75 | } |
| 76 | printk(BIOS_DEBUG, "Locked SMM_FEATURE_CONTROL on %zd sockets\n", found); |
| 77 | if (!found) |
| 78 | printk(BIOS_ERR, "Failed to lock SMM_FEATURE_CONTROL\n"); |
Tim Chu | 3ba1621 | 2022-12-14 11:27:52 +0000 | [diff] [blame] | 79 | } |
| 80 | |
| 81 | /* |
| 82 | * This is the generic entry for SOC SMIs |
| 83 | */ |
| 84 | void cpu_smi_handler(void) |
| 85 | { |
Marc Jones | 352ca5b | 2021-03-18 17:01:06 -0600 | [diff] [blame] | 86 | |
| 87 | } |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 88 | |
| 89 | /* This is needed by common SMM code */ |
| 90 | const smi_handler_t southbridge_smi[SMI_STS_BITS] = { |
| 91 | [APM_STS_BIT] = smihandler_southbridge_apmc, |
| 92 | [PM1_STS_BIT] = smihandler_southbridge_pm1, |
| 93 | #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) |
| 94 | [TCO_STS_BIT] = smihandler_southbridge_tco, |
| 95 | #endif |
| 96 | }; |