Marc Jones | ccfaf25 | 2020-09-28 12:06:36 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpi_gnvs.h> |
| 4 | #include <acpi/acpigen.h> |
| 5 | #include <arch/smp/mpspec.h> |
| 6 | #include <assert.h> |
| 7 | #include <cbmem.h> |
| 8 | #include <cpu/intel/turbo.h> |
| 9 | #include <device/mmio.h> |
| 10 | #include <device/pci.h> |
| 11 | #include <intelblocks/acpi.h> |
| 12 | #include <soc/acpi.h> |
| 13 | #include <soc/cpu.h> |
| 14 | #include <soc/iomap.h> |
| 15 | #include <device/mmio.h> |
| 16 | #include <soc/msr.h> |
| 17 | #include <soc/pci_devs.h> |
| 18 | #include <soc/pm.h> |
| 19 | #include <soc/soc_util.h> |
| 20 | |
Marc Jones | ccfaf25 | 2020-09-28 12:06:36 -0600 | [diff] [blame] | 21 | /* TODO: Check if the common/acpi weak function can be used */ |
| 22 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 23 | { |
| 24 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 25 | CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); |
| 26 | return current; |
| 27 | } |
| 28 | |
| 29 | void acpi_init_gnvs(struct global_nvs *gnvs) |
| 30 | { |
| 31 | /* CPU core count */ |
| 32 | gnvs->pcnt = dev_count_cpu(); |
| 33 | printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); |
| 34 | |
| 35 | /* Update the mem console pointer. */ |
| 36 | if (CONFIG(CONSOLE_CBMEM)) |
| 37 | gnvs->cbmc = (uint32_t)cbmem_find(CBMEM_ID_CONSOLE); |
| 38 | } |
| 39 | |
| 40 | int soc_madt_sci_irq_polarity(int sci) |
| 41 | { |
| 42 | if (sci >= 20) |
| 43 | return MP_IRQ_POLARITY_LOW; |
| 44 | else |
| 45 | return MP_IRQ_POLARITY_HIGH; |
| 46 | } |
| 47 | |
| 48 | uint32_t soc_read_sci_irq_select(void) |
| 49 | { |
| 50 | struct device *dev = PCH_DEV_PMC; |
| 51 | |
| 52 | if (!dev) |
| 53 | return 0; |
| 54 | |
| 55 | return pci_read_config32(dev, PMC_ACPI_CNT); |
| 56 | } |
| 57 | |
Marc Jones | 3fc0484 | 2020-10-19 16:08:27 -0600 | [diff] [blame] | 58 | void soc_fill_fadt(acpi_fadt_t *fadt) |
| 59 | { |
| 60 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 61 | |
| 62 | /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ |
| 63 | fadt->flags &= ~(ACPI_FADT_SEALED_CASE); |
| 64 | fadt->flags |= ACPI_FADT_SLEEP_TYPE; |
| 65 | |
| 66 | fadt->pm2_cnt_blk = pmbase + PM2_CNT; |
| 67 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 68 | |
| 69 | fadt->pm2_cnt_len = 1; |
| 70 | fadt->pm_tmr_len = 4; |
| 71 | |
| 72 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 73 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 74 | |
| 75 | fadt->duty_width = 0; |
| 76 | |
| 77 | /* RTC Registers */ |
| 78 | fadt->mon_alrm = 0x00; |
| 79 | fadt->century = 0x00; |
| 80 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 81 | |
| 82 | /* PM2 Control Registers */ |
| 83 | fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 84 | fadt->x_pm2_cnt_blk.bit_width = 8; |
| 85 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 86 | fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 87 | fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; |
| 88 | fadt->x_pm2_cnt_blk.addrh = 0x00; |
| 89 | |
| 90 | /* PM1 Timer Register */ |
| 91 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 92 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 93 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 94 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 95 | fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; |
| 96 | fadt->x_pm_tmr_blk.addrh = 0x00; |
| 97 | |
| 98 | } |
| 99 | |
Marc Jones | 521a03f | 2020-10-19 13:46:59 -0600 | [diff] [blame] | 100 | void uncore_inject_dsdt(const struct device *device) |
Marc Jones | ccfaf25 | 2020-09-28 12:06:36 -0600 | [diff] [blame] | 101 | { |
| 102 | size_t hob_size; |
| 103 | const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; |
| 104 | const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); |
| 105 | assert(hob != NULL && hob_size != 0); |
| 106 | |
| 107 | acpigen_write_scope("\\_SB"); |
| 108 | for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { |
| 109 | IIO_RESOURCE_INSTANCE iio_resource = |
| 110 | hob->PlatformData.IIO_resource[socket]; |
| 111 | for (int stack = 0; stack <= PSTACK2; ++stack) { |
| 112 | const STACK_RES *ri = &iio_resource.StackRes[stack]; |
| 113 | char rtname[16]; |
| 114 | snprintf(rtname, sizeof(rtname), "RT%02x", |
| 115 | (socket*MAX_IIO_STACK)+stack); |
| 116 | |
| 117 | acpigen_write_name(rtname); |
| 118 | printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", |
| 119 | rtname, socket, stack); |
| 120 | |
| 121 | acpigen_write_resourcetemplate_header(); |
| 122 | |
| 123 | /* bus resource */ |
| 124 | acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, |
| 125 | 0x0, (ri->BusLimit - ri->BusBase + 1)); |
| 126 | |
| 127 | // additional io resources on socket 0 bus 0 |
| 128 | if (socket == 0 && stack == 0) { |
| 129 | /* ACPI 6.4.2.5 I/O Port Descriptor */ |
| 130 | acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); |
| 131 | |
| 132 | /* IO decode CF8-CFF */ |
| 133 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, |
| 134 | 0, 0x03B0); |
| 135 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, |
| 136 | 0, 0x0918); |
| 137 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, |
| 138 | 0, 0x000C); |
| 139 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, |
| 140 | 0, 0x0020); |
| 141 | } |
| 142 | |
| 143 | /* IO resource */ |
| 144 | acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, |
| 145 | ri->PciResourceIoLimit, 0x0, |
| 146 | (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); |
| 147 | |
| 148 | // additional mem32 resources on socket 0 bus 0 |
| 149 | if (socket == 0 && stack == 0) { |
| 150 | acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, |
| 151 | (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, |
| 152 | VGA_BASE_SIZE); |
| 153 | acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, |
| 154 | (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, |
| 155 | SPI_BASE_SIZE); |
| 156 | } |
| 157 | |
| 158 | /* Mem32 resource */ |
| 159 | acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, |
| 160 | ri->PciResourceMem32Limit, 0x0, |
| 161 | (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); |
| 162 | |
| 163 | /* Mem64 resource */ |
| 164 | acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, |
| 165 | ri->PciResourceMem64Limit, 0x0, |
| 166 | (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); |
| 167 | |
| 168 | acpigen_write_resourcetemplate_footer(); |
| 169 | } |
| 170 | } |
| 171 | acpigen_pop_len(); |
| 172 | } |
| 173 | |
Marc Jones | 7a25fb8 | 2020-10-19 16:32:05 -0600 | [diff] [blame^] | 174 | void soc_power_states_generation(int core, int cores_per_package) |
| 175 | { |
| 176 | } |
| 177 | |
Marc Jones | ccfaf25 | 2020-09-28 12:06:36 -0600 | [diff] [blame] | 178 | unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) |
| 179 | { |
| 180 | struct device *cpu; |
| 181 | int num_cpus = 0; |
| 182 | |
| 183 | for (cpu = all_devices; cpu; cpu = cpu->next) { |
| 184 | if ((cpu->path.type != DEVICE_PATH_APIC) || |
| 185 | (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { |
| 186 | continue; |
| 187 | } |
| 188 | if (!cpu->enabled) |
| 189 | continue; |
| 190 | current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, |
| 191 | num_cpus, cpu->path.apic.apic_id); |
| 192 | } |
| 193 | |
| 194 | return current; |
| 195 | } |