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review.coreboot.org / coreboot / e339f9505bbf24ba41c37e4277456acad255d09a / . / src / northbridge / intel / haswell / acpi / hostbridge.asl
blob: f0cb86bd2635f9d2d7a4b78ac3de7c75ef0fc115 [file] [log] [blame]
Angel Pons4b429832020-04-02 23:48:50 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]2
Angel Ponsc5381e02020-10-25 12:56:29 +0100[diff] [blame]3Name (_HID, EISAID ("PNP0A08")) // PCIe
4Name (_CID, EISAID ("PNP0A03")) // PCI
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]5
Angel Ponsc5381e02020-10-25 12:56:29 +0100[diff] [blame]6Name (_BBN, 0)
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]7
8Device (MCHC)
9{
Angel Ponsc5381e02020-10-25 12:56:29 +0100[diff] [blame]10 Name (_ADR, 0x00000000) // 0:0.0
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]11
Angel Ponsc5381e02020-10-25 12:56:29 +0100[diff] [blame]12 OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]13 Field (MCHP, DWordAcc, NoLock, Preserve)
14 {
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]15 Offset (0x70), // ME Base Address
16 MEBA, 64,
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]17 Offset (0xa0), // Top of Used Memory
18 TOM, 64,
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]19 Offset (0xbc), // Top of Low Used Memory
20 TLUD, 32,
21 }
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]22}
23
24// Current Resource Settings
Martin Rothfc706432015-08-18 16:56:05 -0600[diff] [blame]25Name (MCRS, ResourceTemplate()
26{
27 // Bus Numbers
28 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
29 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
30
31 // IO Region 0
32 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
33 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
34
35 // PCI Config Space
36 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
37
38 // IO Region 1
39 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
40 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
41
42 // VGA memory (0xa0000-0xbffff)
43 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
44 Cacheable, ReadWrite,
45 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
46 0x00020000,,, ASEG)
47
48 // OPROM reserved (0xc0000-0xc3fff)
49 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
50 Cacheable, ReadWrite,
51 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
52 0x00004000,,, OPR0)
53
54 // OPROM reserved (0xc4000-0xc7fff)
55 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
56 Cacheable, ReadWrite,
57 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
58 0x00004000,,, OPR1)
59
60 // OPROM reserved (0xc8000-0xcbfff)
61 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
62 Cacheable, ReadWrite,
63 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
64 0x00004000,,, OPR2)
65
66 // OPROM reserved (0xcc000-0xcffff)
67 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
68 Cacheable, ReadWrite,
69 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
70 0x00004000,,, OPR3)
71
72 // OPROM reserved (0xd0000-0xd3fff)
73 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
74 Cacheable, ReadWrite,
75 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
76 0x00004000,,, OPR4)
77
78 // OPROM reserved (0xd4000-0xd7fff)
79 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
80 Cacheable, ReadWrite,
81 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
82 0x00004000,,, OPR5)
83
84 // OPROM reserved (0xd8000-0xdbfff)
85 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
86 Cacheable, ReadWrite,
87 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
88 0x00004000,,, OPR6)
89
90 // OPROM reserved (0xdc000-0xdffff)
91 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
92 Cacheable, ReadWrite,
93 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
94 0x00004000,,, OPR7)
95
96 // BIOS Extension (0xe0000-0xe3fff)
97 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
98 Cacheable, ReadWrite,
99 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
100 0x00004000,,, ESG0)
101
102 // BIOS Extension (0xe4000-0xe7fff)
103 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
104 Cacheable, ReadWrite,
105 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
106 0x00004000,,, ESG1)
107
108 // BIOS Extension (0xe8000-0xebfff)
109 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
110 Cacheable, ReadWrite,
111 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
112 0x00004000,,, ESG2)
113
114 // BIOS Extension (0xec000-0xeffff)
115 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
116 Cacheable, ReadWrite,
117 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
118 0x00004000,,, ESG3)
119
120 // System BIOS (0xf0000-0xfffff)
121 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
122 Cacheable, ReadWrite,
123 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
124 0x00010000,,, FSEG)
125
126 // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
127 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
128 Cacheable, ReadWrite,
129 0x00000000, 0x00000000, 0x00000000, 0x00000000,
130 0x00000000,,, PM01)
131
132 // TPM Area (0xfed40000-0xfed44fff)
133 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
134 Cacheable, ReadWrite,
135 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
136 0x00005000,,, TPMR)
137})
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]138
139Method (_CRS, 0, Serialized)
140{
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]141 // Find PCI resource area in MCRS
Angel Ponsc5381e02020-10-25 12:56:29 +0100[diff] [blame]142 CreateDwordField (MCRS, ^PM01._MIN, PMIN)
143 CreateDwordField (MCRS, ^PM01._MAX, PMAX)
144 CreateDwordField (MCRS, ^PM01._LEN, PLEN)
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]145
146 // Fix up PCI memory region
147 // Start with Top of Lower Usable DRAM
Furquan Shaikh506479d2020-06-01 13:27:16 -0700[diff] [blame]148 // Lower 20 bits of TOLUD register need to be masked since they contain lock and
149 // reserved bits.
150 Local0 = ^MCHC.TLUD & (0xfff << 20)
Furquan Shaikh181e2d42020-06-01 13:03:45 -0700[diff] [blame]151 Local1 = ^MCHC.MEBA
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]152
153 // Check if ME base is equal
Furquan Shaikh181e2d42020-06-01 13:03:45 -0700[diff] [blame]154 If (Local0 == Local1) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]155 // Use Top Of Memory instead
Furquan Shaikh506479d2020-06-01 13:27:16 -0700[diff] [blame]156 // Lower 20 bits of TOM register need to be masked since they contain lock and
157 // reserved bits.
158 Local0 = ^MCHC.TOM & (0x7ffff << 20)
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]159 }
160
Furquan Shaikh181e2d42020-06-01 13:03:45 -0700[diff] [blame]161 PMIN = Local0
162 PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
Angel Ponsc5381e02020-10-25 12:56:29 +0100[diff] [blame]163 PLEN = (PMAX - PMIN) + 1
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]164
165 Return (MCRS)
166}
Angel Ponsf239b5a2020-10-25 12:58:32 +0100[diff] [blame]167
168/* Configurable TDP */
169#include "ctdp.asl"