Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 5 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <delay.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 22 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 23 | #include <device/pci_ops.h> |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 24 | #include <string.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 25 | |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 26 | #include "chip.h" |
| 27 | #include "pch.h" |
| 28 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 29 | int pch_silicon_revision(void) |
| 30 | { |
Felix Held | 82bd0c3 | 2016-08-13 23:27:15 +0200 | [diff] [blame] | 31 | static int pch_revision_id = -1; |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 32 | |
Antonello Dettori | dac8240 | 2016-09-02 09:14:39 +0200 | [diff] [blame] | 33 | #ifdef __SIMPLE_DEVICE__ |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 34 | pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 35 | #else |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 36 | struct device *dev = pcidev_on_root(0x1f, 0); |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 37 | #endif |
| 38 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 39 | if (pch_revision_id < 0) |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 40 | pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 41 | return pch_revision_id; |
| 42 | } |
| 43 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 44 | int pch_silicon_type(void) |
| 45 | { |
Felix Held | 82bd0c3 | 2016-08-13 23:27:15 +0200 | [diff] [blame] | 46 | static int pch_type = -1; |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 47 | |
Antonello Dettori | dac8240 | 2016-09-02 09:14:39 +0200 | [diff] [blame] | 48 | #ifdef __SIMPLE_DEVICE__ |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 49 | pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 50 | #else |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 51 | struct device *dev = pcidev_on_root(0x1f, 0); |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 52 | #endif |
| 53 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 54 | if (pch_type < 0) |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 55 | pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 56 | return pch_type; |
| 57 | } |
| 58 | |
| 59 | int pch_silicon_supported(int type, int rev) |
| 60 | { |
| 61 | int cur_type = pch_silicon_type(); |
| 62 | int cur_rev = pch_silicon_revision(); |
| 63 | |
| 64 | switch (type) { |
| 65 | case PCH_TYPE_CPT: |
| 66 | /* CougarPoint minimum revision */ |
| 67 | if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) |
| 68 | return 1; |
| 69 | /* PantherPoint any revision */ |
| 70 | if (cur_type == PCH_TYPE_PPT) |
| 71 | return 1; |
| 72 | break; |
| 73 | |
| 74 | case PCH_TYPE_PPT: |
| 75 | /* PantherPoint minimum revision */ |
| 76 | if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) |
| 77 | return 1; |
| 78 | break; |
| 79 | } |
| 80 | |
| 81 | return 0; |
| 82 | } |
| 83 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 84 | #define IOBP_RETRY 1000 |
| 85 | static inline int iobp_poll(void) |
| 86 | { |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 87 | unsigned int try = IOBP_RETRY; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 88 | u32 data; |
| 89 | |
| 90 | while (try--) { |
| 91 | data = RCBA32(IOBPS); |
| 92 | if ((data & 1) == 0) |
| 93 | return 1; |
| 94 | udelay(10); |
| 95 | } |
| 96 | |
| 97 | printk(BIOS_ERR, "IOBP timeout\n"); |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) |
| 102 | { |
| 103 | u32 data; |
| 104 | |
| 105 | /* Set the address */ |
| 106 | RCBA32(IOBPIRI) = address; |
| 107 | |
| 108 | /* READ OPCODE */ |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 109 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 110 | RCBA32(IOBPS) = IOBPS_RW_BX; |
| 111 | else |
| 112 | RCBA32(IOBPS) = IOBPS_READ_AX; |
| 113 | if (!iobp_poll()) |
| 114 | return; |
| 115 | |
| 116 | /* Read IOBP data */ |
| 117 | data = RCBA32(IOBPD); |
| 118 | if (!iobp_poll()) |
| 119 | return; |
| 120 | |
| 121 | /* Check for successful transaction */ |
| 122 | if ((RCBA32(IOBPS) & 0x6) != 0) { |
| 123 | printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); |
| 124 | return; |
| 125 | } |
| 126 | |
| 127 | /* Update the data */ |
| 128 | data &= andvalue; |
| 129 | data |= orvalue; |
| 130 | |
| 131 | /* WRITE OPCODE */ |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 132 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 133 | RCBA32(IOBPS) = IOBPS_RW_BX; |
| 134 | else |
| 135 | RCBA32(IOBPS) = IOBPS_WRITE_AX; |
| 136 | if (!iobp_poll()) |
| 137 | return; |
| 138 | |
| 139 | /* Write IOBP data */ |
| 140 | RCBA32(IOBPD) = data; |
| 141 | if (!iobp_poll()) |
| 142 | return; |
| 143 | } |
| 144 | |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 145 | #ifndef __SIMPLE_DEVICE__ |
Frans Hendriks | e6bf51f | 2019-05-01 10:48:31 +0200 | [diff] [blame] | 146 | /* Set bit in function disable register to hide this device */ |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 147 | static void pch_hide_devfn(unsigned int devfn) |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 148 | { |
| 149 | switch (devfn) { |
Patrick Rudolph | 403f433 | 2019-07-14 17:43:52 +0200 | [diff] [blame] | 150 | case PCI_DEVFN(20, 0): /* xHCI */ |
| 151 | if (pch_silicon_type() == PCH_TYPE_PPT) { |
| 152 | /* on CPT this bit is reserved */ |
| 153 | RCBA32_OR(FD, PCH_DISABLE_XHCI); |
| 154 | } |
| 155 | break; |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 156 | case PCI_DEVFN(22, 0): /* MEI #1 */ |
| 157 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 158 | break; |
| 159 | case PCI_DEVFN(22, 1): /* MEI #2 */ |
| 160 | RCBA32_OR(FD2, PCH_DISABLE_MEI2); |
| 161 | break; |
| 162 | case PCI_DEVFN(22, 2): /* IDE-R */ |
| 163 | RCBA32_OR(FD2, PCH_DISABLE_IDER); |
| 164 | break; |
| 165 | case PCI_DEVFN(22, 3): /* KT */ |
| 166 | RCBA32_OR(FD2, PCH_DISABLE_KT); |
| 167 | break; |
| 168 | case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ |
Nico Huber | 6760e0b | 2019-11-17 02:34:53 +0100 | [diff] [blame] | 169 | /* BUC is already handled in `early_pch.c`. */ |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 170 | break; |
| 171 | case PCI_DEVFN(26, 0): /* EHCI #2 */ |
| 172 | RCBA32_OR(FD, PCH_DISABLE_EHCI2); |
| 173 | break; |
| 174 | case PCI_DEVFN(27, 0): /* HD Audio Controller */ |
| 175 | RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); |
| 176 | break; |
| 177 | case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ |
| 178 | case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ |
| 179 | case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ |
| 180 | case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ |
| 181 | case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ |
| 182 | case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ |
| 183 | case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ |
| 184 | case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ |
| 185 | RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn))); |
| 186 | break; |
| 187 | case PCI_DEVFN(29, 0): /* EHCI #1 */ |
| 188 | RCBA32_OR(FD, PCH_DISABLE_EHCI1); |
| 189 | break; |
| 190 | case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ |
| 191 | RCBA32_OR(FD, PCH_DISABLE_P2P); |
| 192 | break; |
| 193 | case PCI_DEVFN(31, 0): /* LPC */ |
| 194 | RCBA32_OR(FD, PCH_DISABLE_LPC); |
| 195 | break; |
| 196 | case PCI_DEVFN(31, 2): /* SATA #1 */ |
| 197 | RCBA32_OR(FD, PCH_DISABLE_SATA1); |
| 198 | break; |
| 199 | case PCI_DEVFN(31, 3): /* SMBUS */ |
| 200 | RCBA32_OR(FD, PCH_DISABLE_SMBUS); |
| 201 | break; |
| 202 | case PCI_DEVFN(31, 5): /* SATA #22 */ |
| 203 | RCBA32_OR(FD, PCH_DISABLE_SATA2); |
| 204 | break; |
| 205 | case PCI_DEVFN(31, 6): /* Thermal Subsystem */ |
| 206 | RCBA32_OR(FD, PCH_DISABLE_THERMAL); |
| 207 | break; |
| 208 | } |
| 209 | } |
| 210 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 211 | /* Check if any port in set X to X+3 is enabled */ |
Elyes HAOUAS | dc03528 | 2018-09-18 13:28:49 +0200 | [diff] [blame] | 212 | static int pch_pcie_check_set_enabled(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 213 | { |
Elyes HAOUAS | dc03528 | 2018-09-18 13:28:49 +0200 | [diff] [blame] | 214 | struct device *port; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 215 | int port_func; |
| 216 | int dev_func = PCI_FUNC(dev->path.pci.devfn); |
| 217 | |
| 218 | printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); |
| 219 | |
| 220 | /* Go through static device tree list of devices |
| 221 | * because enumeration is still in progress */ |
| 222 | for (port = all_devices; port; port = port->next) { |
| 223 | /* Only care about PCIe root ports */ |
| 224 | if (PCI_SLOT(port->path.pci.devfn) != |
| 225 | PCI_SLOT(dev->path.pci.devfn)) |
| 226 | continue; |
| 227 | |
| 228 | /* Check if port is in range and enabled */ |
| 229 | port_func = PCI_FUNC(port->path.pci.devfn); |
| 230 | if (port_func >= dev_func && |
| 231 | port_func < (dev_func + 4) && |
| 232 | port->enabled) |
| 233 | return 1; |
| 234 | } |
| 235 | |
| 236 | /* None of the ports in this set are enabled */ |
| 237 | return 0; |
| 238 | } |
| 239 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 240 | /* RPFN is a write-once register so keep a copy until it is written */ |
| 241 | static u32 new_rpfn; |
| 242 | |
| 243 | /* Swap function numbers assigned to two PCIe Root Ports */ |
| 244 | static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 245 | { |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 246 | u32 old_rpfn = new_rpfn; |
| 247 | |
| 248 | printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", |
| 249 | old_fn, new_fn); |
| 250 | |
| 251 | new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn)); |
| 252 | |
| 253 | /* Old function set to new function and disabled */ |
| 254 | new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn)); |
| 255 | new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn)); |
| 256 | } |
| 257 | |
| 258 | /* Update devicetree with new Root Port function number assignment */ |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 259 | static void pch_pcie_devicetree_update( |
| 260 | struct southbridge_intel_bd82x6x_config *config) |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 261 | { |
Elyes HAOUAS | dc03528 | 2018-09-18 13:28:49 +0200 | [diff] [blame] | 262 | struct device *dev; |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 263 | |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 264 | /* |
| 265 | * hotplug map should also be updated along with their |
| 266 | * corresponding port |
| 267 | */ |
| 268 | u8 new_hotplug_map[sizeof(config->pcie_hotplug_map)]; |
| 269 | |
| 270 | /* |
| 271 | * Slots that didn't move need the hotplug setting copied too, |
| 272 | * so "new_hotplug_map" is initialized with the values of the old map. |
| 273 | */ |
| 274 | memcpy(new_hotplug_map, config->pcie_hotplug_map, |
| 275 | sizeof(new_hotplug_map)); |
| 276 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 277 | /* Update the function numbers in the static devicetree */ |
| 278 | for (dev = all_devices; dev; dev = dev->next) { |
| 279 | u8 new_devfn; |
| 280 | |
| 281 | /* Only care about PCH PCIe root ports */ |
| 282 | if (PCI_SLOT(dev->path.pci.devfn) != |
| 283 | PCH_PCIE_DEV_SLOT) |
| 284 | continue; |
| 285 | |
| 286 | /* Determine the new devfn for this port */ |
| 287 | new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, |
| 288 | RPFN_FNGET(new_rpfn, |
| 289 | PCI_FUNC(dev->path.pci.devfn))); |
| 290 | |
| 291 | if (dev->path.pci.devfn != new_devfn) { |
| 292 | printk(BIOS_DEBUG, |
| 293 | "PCH: PCIe map %02x.%1x -> %02x.%1x\n", |
| 294 | PCI_SLOT(dev->path.pci.devfn), |
| 295 | PCI_FUNC(dev->path.pci.devfn), |
| 296 | PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); |
| 297 | |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 298 | /* |
| 299 | * Copy the flag to its new position along with |
| 300 | * the corresponding port |
| 301 | */ |
| 302 | new_hotplug_map[PCI_FUNC(new_devfn)] = |
| 303 | config->pcie_hotplug_map |
| 304 | [PCI_FUNC(dev->path.pci.devfn)]; |
| 305 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 306 | dev->path.pci.devfn = new_devfn; |
| 307 | } |
| 308 | } |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 309 | |
| 310 | /* Copy the updated map back to its place */ |
| 311 | memcpy(config->pcie_hotplug_map, new_hotplug_map, |
| 312 | sizeof(new_hotplug_map)); |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 313 | } |
| 314 | |
| 315 | /* Special handling for PCIe Root Port devices */ |
Elyes HAOUAS | dc03528 | 2018-09-18 13:28:49 +0200 | [diff] [blame] | 316 | static void pch_pcie_enable(struct device *dev) |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 317 | { |
| 318 | struct southbridge_intel_bd82x6x_config *config = dev->chip_info; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 319 | u32 reg32; |
| 320 | |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 321 | if (!config) |
| 322 | return; |
| 323 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 324 | /* |
| 325 | * Save a copy of the Root Port Function Number map when |
| 326 | * starting to walk the list of PCIe Root Ports so it can |
| 327 | * be updated locally and written out when the last port |
| 328 | * has been processed. |
| 329 | */ |
| 330 | if (PCI_FUNC(dev->path.pci.devfn) == 0) { |
| 331 | new_rpfn = RCBA32(RPFN); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 332 | |
| 333 | /* |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 334 | * Enable Root Port coalescing if the first port is disabled |
| 335 | * or the other devices will not be enumerated by the OS. |
| 336 | */ |
| 337 | if (!dev->enabled) |
| 338 | config->pcie_port_coalesce = 1; |
| 339 | |
| 340 | if (config->pcie_port_coalesce) |
| 341 | printk(BIOS_INFO, |
| 342 | "PCH: PCIe Root Port coalescing is enabled\n"); |
| 343 | } |
| 344 | |
| 345 | if (!dev->enabled) { |
Marc Jones | ef6b08c | 2012-06-15 23:03:15 -0600 | [diff] [blame] | 346 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 347 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 348 | /* |
| 349 | * PCIE Power Savings for PantherPoint and CougarPoint/B1+ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 350 | * |
| 351 | * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 |
| 352 | * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 |
| 353 | * |
| 354 | * This check is done here instead of pcie driver |
| 355 | * because the pcie driver enable() handler is not |
| 356 | * called unless the device is enabled. |
| 357 | */ |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 358 | if ((PCI_FUNC(dev->path.pci.devfn) == 0 || |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 359 | PCI_FUNC(dev->path.pci.devfn) == 4)) { |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 360 | /* Handle workaround for PPT and CPT/B1+ */ |
| 361 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) && |
| 362 | !pch_pcie_check_set_enabled(dev)) { |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 363 | u8 reg8 = pci_read_config8(dev, 0xe2); |
| 364 | reg8 |= 1; |
| 365 | pci_write_config8(dev, 0xe2, reg8); |
| 366 | } |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 367 | |
| 368 | /* |
| 369 | * Enable Clock Gating for shared PCIe resources |
| 370 | * before disabling this particular port. |
| 371 | */ |
| 372 | pci_write_config8(dev, 0xe1, 0x3c); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 373 | } |
| 374 | |
| 375 | /* Ensure memory, io, and bus master are all disabled */ |
| 376 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 377 | reg32 &= ~(PCI_COMMAND_MASTER | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 378 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 379 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 380 | |
| 381 | /* Do not claim downstream transactions for PCIe ports */ |
| 382 | new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); |
| 383 | |
| 384 | /* Hide this device if possible */ |
| 385 | pch_hide_devfn(dev->path.pci.devfn); |
| 386 | } else { |
| 387 | int fn; |
| 388 | |
| 389 | /* |
| 390 | * Check if there is a lower disabled port to swap with this |
| 391 | * port in order to maintain linear order starting at zero. |
| 392 | */ |
| 393 | if (config->pcie_port_coalesce) { |
| 394 | for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { |
| 395 | if (!(new_rpfn & RPFN_HIDE(fn))) |
| 396 | continue; |
| 397 | |
| 398 | /* Swap places with this function */ |
| 399 | pch_pcie_function_swap( |
| 400 | PCI_FUNC(dev->path.pci.devfn), fn); |
| 401 | break; |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | /* Enable SERR */ |
| 406 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 407 | reg32 |= PCI_COMMAND_SERR; |
| 408 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 409 | } |
| 410 | |
| 411 | /* |
| 412 | * When processing the last PCIe root port we can now |
| 413 | * update the Root Port Function Number and Hide register. |
| 414 | */ |
| 415 | if (PCI_FUNC(dev->path.pci.devfn) == 7) { |
| 416 | printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", |
| 417 | RCBA32(RPFN), new_rpfn); |
| 418 | RCBA32(RPFN) = new_rpfn; |
| 419 | |
| 420 | /* Update static devictree with new function numbers */ |
| 421 | if (config->pcie_port_coalesce) |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 422 | pch_pcie_devicetree_update(config); |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 423 | } |
| 424 | } |
| 425 | |
Elyes HAOUAS | dc03528 | 2018-09-18 13:28:49 +0200 | [diff] [blame] | 426 | void pch_enable(struct device *dev) |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 427 | { |
| 428 | u32 reg32; |
| 429 | |
| 430 | /* PCH PCIe Root Ports get special handling */ |
| 431 | if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) |
| 432 | return pch_pcie_enable(dev); |
| 433 | |
| 434 | if (!dev->enabled) { |
| 435 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 436 | |
| 437 | /* Ensure memory, io, and bus master are all disabled */ |
| 438 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 439 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 440 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 441 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 442 | |
| 443 | /* Hide this device if possible */ |
| 444 | pch_hide_devfn(dev->path.pci.devfn); |
| 445 | } else { |
| 446 | /* Enable SERR */ |
| 447 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 448 | reg32 |= PCI_COMMAND_SERR; |
| 449 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 450 | } |
| 451 | } |
| 452 | |
| 453 | struct chip_operations southbridge_intel_bd82x6x_ops = { |
Stefan Reinauer | 9ca1c0a | 2012-07-25 16:10:36 -0700 | [diff] [blame] | 454 | CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 455 | .enable_dev = pch_enable, |
| 456 | }; |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 457 | #endif |