Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 1 | config SOC_UCB_RISCV |
Ronald G. Minnich | 0535804 | 2018-12-19 17:52:43 -0800 | [diff] [blame] | 2 | select ARCH_RISCV_S |
3 | select ARCH_RISCV_U | ||||
4 | select ARCH_RISCV_PMP | ||||
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 5 | select ARCH_BOOTBLOCK_RISCV |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 6 | select ARCH_VERSTAGE_RISCV |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 7 | select ARCH_ROMSTAGE_RISCV |
8 | select ARCH_RAMSTAGE_RISCV | ||||
Philipp Hug | 199b75f | 2018-09-13 18:11:56 +0200 | [diff] [blame] | 9 | select RISCV_USE_ARCH_TIMER |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 10 | bool |
11 | default n | ||||
12 | |||||
13 | if SOC_UCB_RISCV | ||||
14 | |||||
Philipp Hug | b09e500 | 2019-02-06 06:48:51 +0100 | [diff] [blame] | 15 | if ARCH_RISCV_RV64 |
16 | |||||
Xiang Wang | 5fed693 | 2018-07-12 14:56:05 +0800 | [diff] [blame] | 17 | config RISCV_ARCH |
18 | string | ||||
19 | default "rv64imafd" | ||||
20 | |||||
21 | config RISCV_ABI | ||||
22 | string | ||||
23 | default "lp64d" | ||||
24 | |||||
25 | config RISCV_CODEMODEL | ||||
26 | string | ||||
27 | default "medany" | ||||
28 | |||||
Philipp Hug | b09e500 | 2019-02-06 06:48:51 +0100 | [diff] [blame] | 29 | endif |
30 | |||||
31 | if ARCH_RISCV_RV32 | ||||
32 | |||||
33 | config RISCV_ARCH | ||||
34 | string | ||||
35 | default "rv32im" | ||||
36 | |||||
37 | config RISCV_ABI | ||||
38 | string | ||||
39 | default "ilp32" | ||||
40 | |||||
41 | config RISCV_CODEMODEL | ||||
42 | string | ||||
43 | default "medany" | ||||
44 | |||||
45 | endif | ||||
46 | |||||
Xiang Wang | 7c9540e | 2018-10-11 17:30:37 +0800 | [diff] [blame] | 47 | config RISCV_WORKING_HARTID |
48 | int | ||||
49 | default 0 | ||||
50 | |||||
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 51 | endif |