Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 2 | |
| 3 | #include <arch/mmu.h> |
Furquan Shaikh | 8b38519 | 2015-08-05 17:03:34 -0700 | [diff] [blame] | 4 | #include <assert.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 5 | #include <soc/addressmap.h> |
| 6 | #include <soc/mmu_operations.h> |
Julius Werner | fe4cbf1 | 2015-10-07 18:38:24 -0700 | [diff] [blame] | 7 | #include <symbols.h> |
Elyes HAOUAS | 3081855 | 2019-06-23 07:03:59 +0200 | [diff] [blame] | 8 | #include <types.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 9 | |
Julius Werner | fe4cbf1 | 2015-10-07 18:38:24 -0700 | [diff] [blame] | 10 | static void tegra210_mmu_config(void) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 11 | { |
Jacob Garber | 0c4ed4b | 2019-07-04 12:55:35 -0600 | [diff] [blame] | 12 | uintptr_t start, end; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 13 | const unsigned long devmem = MA_DEV | MA_S | MA_RW; |
| 14 | const unsigned long cachedmem = MA_MEM | MA_NS | MA_RW; |
| 15 | const unsigned long secure_mem = MA_MEM | MA_S | MA_RW; |
| 16 | uintptr_t tz_base_mib; |
| 17 | size_t tz_size_mib; |
| 18 | |
| 19 | print_carveouts(); |
| 20 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 21 | memory_in_range_below_4gb(&start,&end); |
| 22 | |
| 23 | /* Device memory below DRAM */ |
Julius Werner | fe4cbf1 | 2015-10-07 18:38:24 -0700 | [diff] [blame] | 24 | mmu_config_range((void *)TEGRA_ARM_LOWEST_PERIPH, start * MiB, devmem); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 25 | |
| 26 | /* DRAM */ |
Julius Werner | fe4cbf1 | 2015-10-07 18:38:24 -0700 | [diff] [blame] | 27 | mmu_config_range((void *)(start * MiB), (end-start) * MiB, cachedmem); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 28 | |
| 29 | memory_in_range_above_4gb(&start,&end); |
| 30 | |
Julius Werner | fe4cbf1 | 2015-10-07 18:38:24 -0700 | [diff] [blame] | 31 | mmu_config_range((void *)(start * MiB), (end-start) * MiB, cachedmem); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 32 | |
| 33 | /* SRAM */ |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 34 | mmu_config_range(_sram, REGION_SIZE(sram), cachedmem); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 35 | |
| 36 | /* Add TZ carveout. */ |
| 37 | carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 38 | |
Julius Werner | fe4cbf1 | 2015-10-07 18:38:24 -0700 | [diff] [blame] | 39 | mmu_config_range((void *)(tz_base_mib * MiB), |
| 40 | tz_size_mib * MiB, secure_mem); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 41 | } |
| 42 | |
| 43 | void tegra210_mmu_init(void) |
| 44 | { |
| 45 | uintptr_t tz_base_mib; |
| 46 | size_t tz_size_mib; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 47 | |
Julius Werner | fe4cbf1 | 2015-10-07 18:38:24 -0700 | [diff] [blame] | 48 | mmu_init(); |
| 49 | tegra210_mmu_config(); |
Furquan Shaikh | 8b38519 | 2015-08-05 17:03:34 -0700 | [diff] [blame] | 50 | /* |
Julius Werner | fe4cbf1 | 2015-10-07 18:38:24 -0700 | [diff] [blame] | 51 | * Page tables are at the end of the trust zone region, but we should |
| 52 | * double-check that memlayout and addressmap.c are in sync. |
| 53 | * |
Furquan Shaikh | 8b38519 | 2015-08-05 17:03:34 -0700 | [diff] [blame] | 54 | * TZDRAM layout is as follows: |
| 55 | * |
| 56 | * +--------------------------+ <----+DRAM_END |
| 57 | * | | |
| 58 | * | | |
| 59 | * | | |
| 60 | * +--------------------------+ <----+0x100000000 |
| 61 | * | | |
| 62 | * | coreboot page tables | |
| 63 | * +--------------------------+ |
| 64 | * | | |
| 65 | * | BL32 | |
| 66 | * +--------------------------+ |
| 67 | * | | |
| 68 | * | BL31 | |
| 69 | * +--------------------------+ <----+TZDRAM_BASE |
| 70 | * | | |
| 71 | * | | |
| 72 | * | | |
| 73 | * | | |
| 74 | * +--------------------------+ <----+DRAM_BASE |
| 75 | * |
| 76 | */ |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 77 | carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 78 | assert((uintptr_t)_ttb + REGION_SIZE(ttb) == (tz_base_mib + tz_size_mib) |
| 79 | * MiB && REGION_SIZE(ttb) <= tz_size_mib * MiB); |
Furquan Shaikh | 8b38519 | 2015-08-05 17:03:34 -0700 | [diff] [blame] | 80 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 81 | mmu_enable(); |
| 82 | } |