Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 2 | |
| 3 | #include <arch/exception.h> |
| 4 | #include <arch/hlt.h> |
Stefan Reinauer | a9bc3bf | 2015-07-09 00:18:03 +0200 | [diff] [blame] | 5 | #include <arch/stages.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 6 | #include <bootblock_common.h> |
| 7 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Yen Lin | a501a8f | 2015-05-06 18:08:22 -0700 | [diff] [blame] | 9 | #include <delay.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 10 | #include <program_loading.h> |
| 11 | #include <soc/addressmap.h> |
| 12 | #include <soc/clock.h> |
| 13 | #include <soc/nvidia/tegra/apbmisc.h> |
| 14 | #include <soc/pmc.h> |
| 15 | #include <soc/power.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 16 | |
Yen Lin | 5e03cd5 | 2015-05-29 16:47:30 -0700 | [diff] [blame] | 17 | #define BCT_OFFSET_IN_BIT 0x4c |
| 18 | #define ODMDATA_OFFSET_IN_BCT 0x508 |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 19 | #define TEGRA_SRAM_MAX (TEGRA_SRAM_BASE + TEGRA_SRAM_SIZE) |
| 20 | |
Asami Doi | 4444369 | 2019-07-12 12:46:02 +0900 | [diff] [blame] | 21 | /* called from assembly in bootblock_asm.S */ |
| 22 | void tegra210_main(void); |
| 23 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 24 | static void save_odmdata(void) |
| 25 | { |
| 26 | struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; |
| 27 | uintptr_t bct_offset; |
| 28 | u32 odmdata; |
| 29 | |
| 30 | // pmc.odmdata: [18:19]: console type, [15:17]: UART id. |
| 31 | // TODO(twarren) ODMDATA is stored in the BCT, from bct/odmdata.cfg. |
| 32 | // I use the BCT offset in the BIT in SRAM to locate the BCT, and |
| 33 | // pick up the ODMDATA word at BCT offset 0x6A8. I could use a BCT |
| 34 | // struct header from cbootimage, but it seems like overkill for this. |
| 35 | |
| 36 | bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT)); |
| 37 | if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) { |
| 38 | odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT)); |
| 39 | write32(&pmc->odmdata, odmdata); |
| 40 | } |
| 41 | } |
| 42 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 43 | void __weak bootblock_mainboard_early_init(void) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 44 | { |
| 45 | /* Empty default implementation. */ |
| 46 | } |
| 47 | |
Yen Lin | a501a8f | 2015-05-06 18:08:22 -0700 | [diff] [blame] | 48 | /* |
| 49 | * Define operations for the workaround: |
| 50 | * OP_SET : [reg] = val; |
| 51 | * OP_OR : [reg] |= val; |
| 52 | * OP_AND : [reg] &= val; |
| 53 | * OP_UDELAY : udelay(val); |
| 54 | */ |
| 55 | typedef enum { |
| 56 | OP_SET, |
| 57 | OP_OR, |
| 58 | OP_AND, |
| 59 | OP_UDELAY, /* use val field as usec delay */ |
| 60 | } WAR_OP; |
| 61 | |
| 62 | struct workaround_op { |
| 63 | WAR_OP op; |
| 64 | u32 reg; |
| 65 | u32 val; |
| 66 | }; |
| 67 | |
| 68 | /* |
| 69 | * An array defines the sequence to perform the workaround |
| 70 | */ |
| 71 | static struct workaround_op workaround_sequence[] = { |
| 72 | {OP_OR, 0x60006410, (1 << 15)}, /* CLK_SOURCE_SOR1: */ |
| 73 | {OP_AND, 0x60006410, ~(1 << 14)}, /* CLK_SEL1=1, CLK_SEL0=0 */ |
| 74 | {OP_OR, 0x600060d0, 0x40800000}, /* PLLD_BASE */ |
| 75 | {OP_SET, 0x600062ac, 0x40}, /* clear APE reset */ |
| 76 | {OP_SET, 0x60006294, 0x40000}, /* clear VIC reset */ |
| 77 | {OP_SET, 0x60006304, 0x18000000}, /* clear HOST1X & DISP1 reset */ |
| 78 | {OP_UDELAY, 0, 2}, |
| 79 | {OP_OR, 0x702d10a0, 0x400}, /* I2S0: I2S_CTRL.MASTER=1 */ |
| 80 | {OP_AND, 0x702d1088, ~1}, /* I2S0: I2S_CG.SLCG_ENABLE=0 */ |
| 81 | {OP_OR, 0x702d11a0, 0x400}, /* I2S1: I2S_CTRL.MASTER=1 */ |
| 82 | {OP_AND, 0x702d1188, ~1}, /* I2S1: I2S_CG.SLCG_ENABLE=0 */ |
| 83 | {OP_OR, 0x702d12a0, 0x400}, /* I2S2: I2S_CTRL.MASTER=1 */ |
| 84 | {OP_AND, 0x702d1288, ~1}, /* I2S2: I2S_CG.SLCG_ENABLE=0 */ |
| 85 | {OP_OR, 0x702d13a0, 0x400}, /* I2S3: I2S_CTRL.MASTER=1 */ |
| 86 | {OP_AND, 0x702d1388, ~1}, /* I2S3: I2S_CG.SLCG_ENABLE=0 */ |
| 87 | {OP_OR, 0x702d14a0, 0x400}, /* I2S4: I2S_CTRL.MASTER=1 */ |
| 88 | {OP_AND, 0x702d1488, ~1}, /* I2S4: I2S_CG.SLCG_ENABLE=0 */ |
| 89 | {OP_OR, 0x54200cf8, 4}, /* DC_COM_DSC_TOP_CTL[DSC_SLCG_OVERRIDE]=1 */ |
| 90 | {OP_SET, 0x543400c8, 0xffffffff}, /* NV_PVIC_THI_SLCG_OVERRIDE_LOW_A = 0xFFFF_FFFF */ |
| 91 | {OP_UDELAY, 0, 2}, |
| 92 | {OP_SET, 0x600062a8, 0x40}, /* set APE reset */ |
| 93 | {OP_SET, 0x60006300, 0x18000000}, /* set HOST1X & DISP1 reset */ |
| 94 | {OP_SET, 0x60006290, 0x40000}, /* set VIC reset */ |
| 95 | {OP_SET, 0x60006014, 0x020000c1}, /* CLK_ENB_H */ |
| 96 | {OP_SET, 0x60006010, 0x80400130}, /* CLK_ENB_L */ |
| 97 | {OP_SET, 0x60006018, 0x01f00200}, /* CLK_ENB_U */ |
| 98 | {OP_SET, 0x60006360, 0x80400808}, /* CLK_ENB_V */ |
| 99 | {OP_SET, 0x60006364, 0x402000fc}, /* CLK_ENB_W */ |
| 100 | {OP_SET, 0x60006280, 0x23000780}, /* CLK_ENB_X */ |
| 101 | {OP_SET, 0x60006298, 0x00000340}, /* CLK_ENB_Y */ |
| 102 | {OP_SET, 0x600060f8, 0x00000000}, /* LVL2_CLK_GATE_OVRA */ |
| 103 | {OP_SET, 0x600060fc, 0x00000000}, /* LVL2_CLK_GATE_OVRB */ |
| 104 | {OP_SET, 0x600063a0, 0x00000000}, /* LVL2_CLK_GATE_OVRC */ |
| 105 | {OP_SET, 0x600063a4, 0x01000000}, /* LVL2_CLK_GATE_OVRD, QSPI_CLK_OVR_ON=1 */ |
| 106 | {OP_SET, 0x60006554, 0x00000000}, /* LVL2_CLK_GATE_OVRE */ |
| 107 | {OP_AND, 0x600060d0, 0x1f7fffff}, /* PLLD_BASE: 31,30,29,23 = 0 */ |
| 108 | {OP_AND, 0x60006410, 0xffff3fff}, /* CLK_SOURCE_SOR1 15,14 = 0 */ |
| 109 | {OP_AND, 0x60006148, ~(7 << 29)}, /* CLK_SOURCE_VI: */ |
| 110 | {OP_OR, 0x60006148, (4 << 29)}, /* SRC=PLLP_OUT0 (4) */ |
| 111 | {OP_AND, 0x60006180, ~(7 << 29)}, /* CLK_SOURCE_HOST1X: */ |
| 112 | {OP_OR, 0x60006180, (4 << 29)}, /* SRC=PLLP_OUT0 (4) */ |
| 113 | {OP_AND, 0x600066a0, ~(7 << 29)}, /* CLK_SOURCE_NVENC: */ |
| 114 | {OP_OR, 0x600066a0, (4 << 29)} /* SRC=PLLP_OUT0 (4) */ |
| 115 | }; |
| 116 | |
| 117 | /* |
| 118 | * This workaround is to restore CAR CE's, SLCG overrides & PLLD settings |
| 119 | */ |
| 120 | static void mbist_workaround(void) |
| 121 | { |
| 122 | int i; |
| 123 | u32 val; |
| 124 | struct workaround_op *wa_op; |
| 125 | |
| 126 | for (i = 0; i < ARRAY_SIZE(workaround_sequence); ++i) { |
| 127 | wa_op = &workaround_sequence[i]; |
| 128 | switch (wa_op->op) { |
| 129 | case OP_SET: |
| 130 | val = wa_op->val; |
| 131 | break; |
| 132 | case OP_OR: |
| 133 | val = read32((void *)wa_op->reg) | wa_op->val; |
| 134 | break; |
| 135 | case OP_AND: |
| 136 | val = read32((void *)wa_op->reg) & wa_op->val; |
| 137 | break; |
| 138 | case OP_UDELAY: |
| 139 | udelay(wa_op->val); |
Arthur Heymans | 507b074 | 2022-03-24 01:16:34 +0100 | [diff] [blame] | 140 | __fallthrough; |
Yen Lin | a501a8f | 2015-05-06 18:08:22 -0700 | [diff] [blame] | 141 | default: |
| 142 | continue; |
| 143 | } |
| 144 | write32((void *)wa_op->reg, val); |
| 145 | } |
| 146 | } |
| 147 | |
Asami Doi | 4444369 | 2019-07-12 12:46:02 +0900 | [diff] [blame] | 148 | void tegra210_main(void) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 149 | { |
| 150 | // enable JTAG at the earliest stage |
| 151 | enable_jtag(); |
| 152 | |
Yen Lin | a501a8f | 2015-05-06 18:08:22 -0700 | [diff] [blame] | 153 | mbist_workaround(); |
| 154 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 155 | clock_early_uart(); |
| 156 | |
| 157 | /* Configure mselect clock. */ |
| 158 | clock_configure_source(mselect, PLLP, 102000); |
| 159 | |
| 160 | /* Enable AVP cache, timer, APB dma, and mselect blocks. */ |
| 161 | clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR, |
| 162 | CLK_H_APBDMA, |
| 163 | 0, CLK_V_MSELECT, 0, 0, 0); |
| 164 | |
| 165 | /* Find ODMDATA in IRAM and save it to scratch reg */ |
| 166 | save_odmdata(); |
| 167 | |
| 168 | bootblock_mainboard_early_init(); |
| 169 | |
Julius Werner | 5d1f9a0 | 2019-03-07 17:07:26 -0800 | [diff] [blame] | 170 | if (CONFIG(BOOTBLOCK_CONSOLE)) { |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 171 | console_init(); |
| 172 | exception_init(); |
| 173 | printk(BIOS_INFO, "T210: Bootblock here\n"); |
| 174 | } |
| 175 | |
| 176 | clock_init(); |
| 177 | |
| 178 | printk(BIOS_INFO, "T210 bootblock: Clock init done\n"); |
| 179 | |
| 180 | pmc_print_rst_status(); |
| 181 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 182 | bootblock_mainboard_init(); |
| 183 | |
| 184 | printk(BIOS_INFO, "T210 bootblock: Mainboard bootblock init done\n"); |
| 185 | |
| 186 | run_romstage(); |
| 187 | } |