Martin Roth | 9231f0b | 2022-10-28 22:39:23 -0600 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 2 | ifeq ($(CONFIG_SOC_NVIDIA_TEGRA210),y) |
| 3 | |
| 4 | CBOOTIMAGE_OPTS = --soc tegra210 |
| 5 | |
| 6 | bootblock-y += bootblock.c |
| 7 | bootblock-y += bootblock_asm.S |
| 8 | bootblock-y += clock.c |
| 9 | bootblock-y += spi.c |
| 10 | bootblock-y += i2c.c |
| 11 | bootblock-y += dma.c |
| 12 | bootblock-y += monotonic_timer.c |
| 13 | bootblock-y += padconfig.c |
| 14 | bootblock-y += power.c |
| 15 | bootblock-y += funitcfg.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 16 | bootblock-y += ../tegra/gpio.c |
| 17 | bootblock-y += ../tegra/i2c.c |
| 18 | bootblock-y += ../tegra/pingroup.c |
| 19 | bootblock-y += ../tegra/pinmux.c |
| 20 | bootblock-y += ../tegra/apbmisc.c |
| 21 | bootblock-y += ../tegra/usb.c |
Nico Huber | 755db95 | 2018-11-11 01:42:17 +0100 | [diff] [blame] | 22 | bootblock-y += uart.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 23 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 24 | verstage-y += dma.c |
| 25 | verstage-y += monotonic_timer.c |
| 26 | verstage-y += spi.c |
| 27 | verstage-y += padconfig.c |
| 28 | verstage-y += funitcfg.c |
Nico Huber | 755db95 | 2018-11-11 01:42:17 +0100 | [diff] [blame] | 29 | verstage-y += uart.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 30 | verstage-y += ../tegra/gpio.c |
| 31 | verstage-y += ../tegra/i2c.c |
| 32 | verstage-y += ../tegra/pinmux.c |
| 33 | verstage-y += clock.c |
| 34 | verstage-y += i2c.c |
| 35 | |
| 36 | romstage-y += romstage_asm.S |
| 37 | romstage-y += addressmap.c |
| 38 | romstage-y += cbmem.c |
| 39 | romstage-y += ccplex.c |
| 40 | romstage-y += clock.c |
| 41 | romstage-y += cpu.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 42 | romstage-y += spi.c |
| 43 | romstage-y += i2c.c |
| 44 | romstage-y += dma.c |
| 45 | romstage-y += monotonic_timer.c |
| 46 | romstage-y += padconfig.c |
| 47 | romstage-y += funitcfg.c |
| 48 | romstage-y += romstage.c |
| 49 | romstage-y += power.c |
| 50 | romstage-y += ram_code.c |
| 51 | ifneq ($(CONFIG_BOOTROM_SDRAM_INIT),y) |
| 52 | romstage-y += sdram.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 53 | romstage-y += sdram_lp0.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 54 | endif |
| 55 | romstage-y += ../tegra/gpio.c |
| 56 | romstage-y += ../tegra/i2c.c |
| 57 | romstage-y += ../tegra/pinmux.c |
| 58 | romstage-y += ../tegra/usb.c |
Nico Huber | 755db95 | 2018-11-11 01:42:17 +0100 | [diff] [blame] | 59 | romstage-y += uart.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 60 | |
| 61 | ramstage-y += addressmap.c |
| 62 | ramstage-y += cbmem.c |
| 63 | ramstage-y += cpu.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 64 | ramstage-y += clock.c |
| 65 | ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += dc.c |
| 66 | ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += dsi.c |
| 67 | ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi_dsi.c |
| 68 | ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi.c |
| 69 | ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi-phy.c |
| 70 | ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += ./jdi_25x18_display/panel-jdi-lpm102a188a.c |
| 71 | ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += dp.c |
| 72 | ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += sor.c |
Furquan Shaikh | f814215 | 2015-08-05 17:05:26 -0700 | [diff] [blame] | 73 | ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 74 | |
Yen Lin | ae3d71a | 2015-06-01 15:32:09 -0700 | [diff] [blame] | 75 | ramstage-y += sdram_lp0.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 76 | ramstage-y += soc.c |
| 77 | ramstage-y += spi.c |
| 78 | ramstage-y += i2c.c |
| 79 | ramstage-y += i2c6.c |
| 80 | ramstage-y += ape.c |
| 81 | ramstage-y += power.c |
| 82 | ramstage-y += dma.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 83 | ramstage-y += monotonic_timer.c |
| 84 | ramstage-y += padconfig.c |
| 85 | ramstage-y += funitcfg.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 86 | ramstage-y += ram_code.c |
| 87 | ramstage-y += ../tegra/apbmisc.c |
| 88 | ramstage-y += ../tegra/gpio.c |
| 89 | ramstage-y += ../tegra/i2c.c |
| 90 | ramstage-y += ../tegra/pinmux.c |
| 91 | ramstage-y += ramstage.c |
| 92 | ramstage-y += mmu_operations.c |
Nico Huber | 755db95 | 2018-11-11 01:42:17 +0100 | [diff] [blame] | 93 | ramstage-y += uart.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 94 | ramstage-y += ../tegra/usb.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 95 | ramstage-$(CONFIG_HAVE_MTC) += mtc.c |
Furquan Shaikh | 25fbe2a | 2015-07-10 15:29:13 -0700 | [diff] [blame] | 96 | ramstage-y += stage_entry.S |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 97 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 98 | rmodules_arm-y += monotonic_timer.c |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 99 | |
| 100 | CPPFLAGS_common += -Isrc/soc/nvidia/tegra210/include/ |
| 101 | |
| 102 | # We want to grab the bootblock right before it goes into the image and wrap |
| 103 | # it inside a BCT, but ideally we would do that without making special, one |
| 104 | # use modifications to the main ARM Makefile. We do this in two ways. First, |
| 105 | # we copy bootblock.elf to bootblock.raw.elf and allow the %.bin: %.elf |
| 106 | # template rule to turn it into bootblock.raw.bin. This makes sure whatever |
| 107 | # processing is supposed to happen to turn an .elf into a .bin happens. |
| 108 | # |
| 109 | # Second, we add our own rule for creating bootblock.bin from |
| 110 | # bootblock.raw.bin which displaces the template rule. When other rules that |
| 111 | # package up the image pull in bootblock.bin, it will be this wrapped version |
| 112 | # instead of the raw bootblock. |
| 113 | |
| 114 | $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf |
| 115 | cp $< $@ |
| 116 | |
| 117 | $(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE) |
| 118 | @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" |
| 119 | $(CBOOTIMAGE) -gbct $(CBOOTIMAGE_OPTS) $< $@ |
| 120 | |
| 121 | BCT_BIN = $(obj)/generated/bct.bin |
| 122 | BCT_WRAPPER = $(obj)/generated/bct.wrapper |
| 123 | $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) |
| 124 | echo "Version = 1;" > $(BCT_WRAPPER) |
| 125 | echo "Redundancy = 1;" >> $(BCT_WRAPPER) |
| 126 | echo "Bctcopy = 1;" >> $(BCT_WRAPPER) |
| 127 | echo "Bctfile = $(BCT_BIN);" >> $(BCT_WRAPPER) |
| 128 | echo "BootLoader = $<,$(call loadaddr,bootblock),$(call loadaddr,bootblock),Complete;" >> $(BCT_WRAPPER) |
| 129 | @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" |
| 130 | $(CBOOTIMAGE) $(CBOOTIMAGE_OPTS) $(BCT_WRAPPER) $@ |
| 131 | |
Furquan Shaikh | 3ae5044 | 2015-07-07 21:35:56 -0700 | [diff] [blame] | 132 | # We need to ensure that TZ memory has enough space to hold TTB and resident EL3 |
| 133 | # components (including BL31 and Secure OS) |
| 134 | ttb_size=$(shell printf "%d" $(CONFIG_TTB_SIZE_MB)) |
| 135 | sec_size=$(shell printf "%d" $(CONFIG_SEC_COMPONENT_SIZE_MB)) |
| 136 | req_tz_size=$(shell expr $(ttb_size) + $(sec_size)) |
| 137 | |
| 138 | tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) |
| 139 | |
| 140 | ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1) |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 141 | $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be at least as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") |
Furquan Shaikh | 3ae5044 | 2015-07-07 21:35:56 -0700 | [diff] [blame] | 142 | endif |
| 143 | |
| 144 | # BL31 component is placed towards the end of 32-bit address space. This assumes |
| 145 | # that TrustZone memory is placed at the end of 32-bit address space. Within the |
Furquan Shaikh | 8b38519 | 2015-08-05 17:03:34 -0700 | [diff] [blame] | 146 | # TZ memory, we place BL31 and BL32(if available) towards the beginning and TTB |
| 147 | # towards the end. Calculate TZDRAM_BASE i.e. base of BL31 component by: |
Furquan Shaikh | 3ae5044 | 2015-07-07 21:35:56 -0700 | [diff] [blame] | 148 | # 0x1000 = end of 32-bit address space in MiB |
| 149 | # 0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) = start of TZ memory in MiB |
Furquan Shaikh | 8b38519 | 2015-08-05 17:03:34 -0700 | [diff] [blame] | 150 | BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) << 20)) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 151 | BL31_MAKEARGS += PLAT=tegra TARGET_SOC=t210 |
| 152 | |
| 153 | # MTC fw |
| 154 | MTC_DIR = $(CONFIG_MTC_DIRECTORY) |
| 155 | MTC_FILE = $(MTC_DIR)/$(CONFIG_MTC_FILE) |
| 156 | MTC_FILE_CBFS = $(CONFIG_MTC_FILE) |
| 157 | cbfs-files-$(CONFIG_HAVE_MTC) += $(MTC_FILE_CBFS) |
| 158 | $(MTC_FILE_CBFS)-file := $(MTC_FILE) |
Martin Roth | 8ea0651 | 2016-09-19 13:58:01 -0600 | [diff] [blame] | 159 | $(MTC_FILE_CBFS)-type := raw |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 160 | |
| 161 | endif |