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review.coreboot.org / coreboot / 799c3219146c8d246ef95f1fdb83dc7bc1f2be61 / . / src / soc / nvidia / tegra210 / Kconfig
blob: 0244b47deffbc3f068596eac468efe9a180a9b0e [file] [log] [blame]
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]1config SOC_NVIDIA_TEGRA210
2 bool
3 default n
4 select ARCH_BOOTBLOCK_ARMV4
Julius Werner86fc11d2015-10-09 13:37:58 -0700[diff] [blame]5 select BOOTBLOCK_CUSTOM
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]6 select ARCH_VERSTAGE_ARMV4
7 select ARCH_ROMSTAGE_ARMV4
8 select ARCH_RAMSTAGE_ARMV8_64
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]9 select HAVE_UART_SPECIAL
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]10 select ARM64_USE_ARM_TRUSTED_FIRMWARE
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]11 select GENERIC_GPIO_LIB
12
13if SOC_NVIDIA_TEGRA210
14
Furquan Shaikh46514c22020-06-11 11:59:07 -0700[diff] [blame]15config MEMLAYOUT_LD_FILE
16 string
17 default "src/soc/nvidia/tegra210/memlayout.ld"
18
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]19config VBOOT
Julius Werner1210b412017-03-27 19:26:32 -0700[diff] [blame]20 select VBOOT_STARTS_IN_BOOTBLOCK
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]21 select VBOOT_SEPARATE_VERSTAGE
Julius Wernera2d123e2019-11-12 15:43:12 -0800[diff] [blame]22 select VBOOT_RETURN_FROM_VERSTAGE
Joel Kitching6672bd82019-04-10 16:06:21 +0800[diff] [blame]23 select VBOOT_MUST_REQUEST_DISPLAY
Martin Roth967cd9a2015-08-18 14:22:58 -0600[diff] [blame]24
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]25config MAINBOARD_DO_DSI_INIT
26 bool "Use dsi graphics interface"
27 depends on MAINBOARD_DO_NATIVE_VGA_INIT
28 default n
Nico Huber7971582e2017-05-20 01:07:48 +0200[diff] [blame]29 select HAVE_LINEAR_FRAMEBUFFER
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]30 help
31 Initialize dsi display
32
33config MAINBOARD_DO_SOR_INIT
34 bool "Use dp graphics interface"
35 depends on MAINBOARD_DO_NATIVE_VGA_INIT
36 default n
Nico Huber7971582e2017-05-20 01:07:48 +0200[diff] [blame]37 select HAVE_LINEAR_FRAMEBUFFER
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]38 help
39 Initialize dp display
40
Martin Rothf924aee2016-11-11 14:24:22 -0700[diff] [blame]41choice
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]42 prompt "Serial Console UART"
43 default CONSOLE_SERIAL_TEGRA210_UARTA
Martin Rothdf02c332015-07-01 23:09:42 -0600[diff] [blame]44 depends on CONSOLE_SERIAL
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]45
46config CONSOLE_SERIAL_TEGRA210_UARTA
47 bool "UARTA"
48 help
49 Serial console on UART A.
50
51config CONSOLE_SERIAL_TEGRA210_UARTB
52 bool "UARTB"
53 help
54 Serial console on UART B.
55
56config CONSOLE_SERIAL_TEGRA210_UARTC
57 bool "UARTC"
58 help
59 Serial console on UART C.
60
61config CONSOLE_SERIAL_TEGRA210_UARTD
62 bool "UARTD"
63 help
64 Serial console on UART D.
65
66config CONSOLE_SERIAL_TEGRA210_UARTE
67 bool "UARTE"
68 help
69 Serial console on UART E.
70
71endchoice
72
73config CONSOLE_SERIAL_TEGRA210_UART_ADDRESS
74 hex
Martin Rothdf02c332015-07-01 23:09:42 -0600[diff] [blame]75 depends on CONSOLE_SERIAL
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]76 default 0x70006000 if CONSOLE_SERIAL_TEGRA210_UARTA
77 default 0x70006040 if CONSOLE_SERIAL_TEGRA210_UARTB
78 default 0x70006200 if CONSOLE_SERIAL_TEGRA210_UARTC
79 default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD
80 default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE
81 help
Martin Roth26f97f92021-10-01 14:53:22 -0600[diff] [blame]82 Map the UART names to the respective MMIO addresses.
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]83
84config BOOTROM_SDRAM_INIT
85 bool "SoC BootROM does SDRAM init with full BCT"
86 default n
87 help
88 Use during Foster LPDDR4 bringup.
89
90config TRUSTZONE_CARVEOUT_SIZE_MB
91 hex "Size of Trust Zone region"
92 default 0x14
93 help
94 Size of Trust Zone area in MiB to reserve in memory map.
95
Furquan Shaikh3ae50442015-07-07 21:35:56 -0700[diff] [blame]96config TTB_SIZE_MB
97 hex "Size of TTB"
98 default 0x4
99 help
100 Maximum size of Translation Table Buffer in MiB.
101
102config SEC_COMPONENT_SIZE_MB
103 hex "Size of resident EL3 components"
104 default 0x10
105 help
106 Maximum size of resident EL3 components in MiB including BL31 and
107 Secure OS.
108
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]109# Default to 700MHz. This value is based on nv bootloader setting.
110config PLLX_KHZ
Martin Roth45895f12015-07-01 19:38:29 -0600[diff] [blame]111 int
112 default 700000
Patrick Georgi40a3e322015-06-22 19:41:29 +0200[diff] [blame]113
114config HAVE_MTC
115 bool "Add external Memory controller Training Code binary"
116 default n
117 depends on USE_BLOBS
118 help
119 Select this option to add emc training firmware
120
121if HAVE_MTC
122
123config MTC_FILE
124 string "tegra mtc firmware filename"
125 default "tegra_mtc.bin"
126 help
127 The filename of the mtc firmware
128
129config MTC_DIRECTORY
130 string "Directory where MTC firmware file is located"
131 default "."
132 help
133 Path to directory where MTC firmware file is located.
134
135config MTC_ADDRESS
136 hex
137 default 0x81000000
138 help
139 The DRAM location where MTC firmware to be loaded in. This location
140 needs to be consistent with the location defined in tegra_mtc.ld
141
142endif # HAVE_MTC
143
Vladimir Serbinenko52262662015-10-11 02:17:21 +0200[diff] [blame]144endif # SOC_NVIDIA_TEGRA210