Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 1 | config SOC_NVIDIA_TEGRA210 |
| 2 | bool |
| 3 | default n |
| 4 | select ARCH_BOOTBLOCK_ARMV4 |
Julius Werner | 86fc11d | 2015-10-09 13:37:58 -0700 | [diff] [blame] | 5 | select BOOTBLOCK_CUSTOM |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 6 | select ARCH_VERSTAGE_ARMV4 |
| 7 | select ARCH_ROMSTAGE_ARMV4 |
| 8 | select ARCH_RAMSTAGE_ARMV8_64 |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 9 | select HAVE_UART_SPECIAL |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 10 | select ARM64_USE_ARM_TRUSTED_FIRMWARE |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 11 | select GENERIC_GPIO_LIB |
| 12 | |
| 13 | if SOC_NVIDIA_TEGRA210 |
| 14 | |
Furquan Shaikh | 46514c2 | 2020-06-11 11:59:07 -0700 | [diff] [blame] | 15 | config MEMLAYOUT_LD_FILE |
| 16 | string |
| 17 | default "src/soc/nvidia/tegra210/memlayout.ld" |
| 18 | |
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 19 | config VBOOT |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 20 | select VBOOT_STARTS_IN_BOOTBLOCK |
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 21 | select VBOOT_SEPARATE_VERSTAGE |
Julius Werner | a2d123e | 2019-11-12 15:43:12 -0800 | [diff] [blame] | 22 | select VBOOT_RETURN_FROM_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 23 | select VBOOT_MUST_REQUEST_DISPLAY |
Martin Roth | 967cd9a | 2015-08-18 14:22:58 -0600 | [diff] [blame] | 24 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 25 | config MAINBOARD_DO_DSI_INIT |
| 26 | bool "Use dsi graphics interface" |
| 27 | depends on MAINBOARD_DO_NATIVE_VGA_INIT |
| 28 | default n |
Nico Huber | 7971582e | 2017-05-20 01:07:48 +0200 | [diff] [blame] | 29 | select HAVE_LINEAR_FRAMEBUFFER |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 30 | help |
| 31 | Initialize dsi display |
| 32 | |
| 33 | config MAINBOARD_DO_SOR_INIT |
| 34 | bool "Use dp graphics interface" |
| 35 | depends on MAINBOARD_DO_NATIVE_VGA_INIT |
| 36 | default n |
Nico Huber | 7971582e | 2017-05-20 01:07:48 +0200 | [diff] [blame] | 37 | select HAVE_LINEAR_FRAMEBUFFER |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 38 | help |
| 39 | Initialize dp display |
| 40 | |
Martin Roth | f924aee | 2016-11-11 14:24:22 -0700 | [diff] [blame] | 41 | choice |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 42 | prompt "Serial Console UART" |
| 43 | default CONSOLE_SERIAL_TEGRA210_UARTA |
Martin Roth | df02c33 | 2015-07-01 23:09:42 -0600 | [diff] [blame] | 44 | depends on CONSOLE_SERIAL |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 45 | |
| 46 | config CONSOLE_SERIAL_TEGRA210_UARTA |
| 47 | bool "UARTA" |
| 48 | help |
| 49 | Serial console on UART A. |
| 50 | |
| 51 | config CONSOLE_SERIAL_TEGRA210_UARTB |
| 52 | bool "UARTB" |
| 53 | help |
| 54 | Serial console on UART B. |
| 55 | |
| 56 | config CONSOLE_SERIAL_TEGRA210_UARTC |
| 57 | bool "UARTC" |
| 58 | help |
| 59 | Serial console on UART C. |
| 60 | |
| 61 | config CONSOLE_SERIAL_TEGRA210_UARTD |
| 62 | bool "UARTD" |
| 63 | help |
| 64 | Serial console on UART D. |
| 65 | |
| 66 | config CONSOLE_SERIAL_TEGRA210_UARTE |
| 67 | bool "UARTE" |
| 68 | help |
| 69 | Serial console on UART E. |
| 70 | |
| 71 | endchoice |
| 72 | |
| 73 | config CONSOLE_SERIAL_TEGRA210_UART_ADDRESS |
| 74 | hex |
Martin Roth | df02c33 | 2015-07-01 23:09:42 -0600 | [diff] [blame] | 75 | depends on CONSOLE_SERIAL |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 76 | default 0x70006000 if CONSOLE_SERIAL_TEGRA210_UARTA |
| 77 | default 0x70006040 if CONSOLE_SERIAL_TEGRA210_UARTB |
| 78 | default 0x70006200 if CONSOLE_SERIAL_TEGRA210_UARTC |
| 79 | default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD |
| 80 | default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE |
| 81 | help |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 82 | Map the UART names to the respective MMIO addresses. |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 83 | |
| 84 | config BOOTROM_SDRAM_INIT |
| 85 | bool "SoC BootROM does SDRAM init with full BCT" |
| 86 | default n |
| 87 | help |
| 88 | Use during Foster LPDDR4 bringup. |
| 89 | |
| 90 | config TRUSTZONE_CARVEOUT_SIZE_MB |
| 91 | hex "Size of Trust Zone region" |
| 92 | default 0x14 |
| 93 | help |
| 94 | Size of Trust Zone area in MiB to reserve in memory map. |
| 95 | |
Furquan Shaikh | 3ae5044 | 2015-07-07 21:35:56 -0700 | [diff] [blame] | 96 | config TTB_SIZE_MB |
| 97 | hex "Size of TTB" |
| 98 | default 0x4 |
| 99 | help |
| 100 | Maximum size of Translation Table Buffer in MiB. |
| 101 | |
| 102 | config SEC_COMPONENT_SIZE_MB |
| 103 | hex "Size of resident EL3 components" |
| 104 | default 0x10 |
| 105 | help |
| 106 | Maximum size of resident EL3 components in MiB including BL31 and |
| 107 | Secure OS. |
| 108 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 109 | # Default to 700MHz. This value is based on nv bootloader setting. |
| 110 | config PLLX_KHZ |
Martin Roth | 45895f1 | 2015-07-01 19:38:29 -0600 | [diff] [blame] | 111 | int |
| 112 | default 700000 |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 113 | |
| 114 | config HAVE_MTC |
| 115 | bool "Add external Memory controller Training Code binary" |
| 116 | default n |
| 117 | depends on USE_BLOBS |
| 118 | help |
| 119 | Select this option to add emc training firmware |
| 120 | |
| 121 | if HAVE_MTC |
| 122 | |
| 123 | config MTC_FILE |
| 124 | string "tegra mtc firmware filename" |
| 125 | default "tegra_mtc.bin" |
| 126 | help |
| 127 | The filename of the mtc firmware |
| 128 | |
| 129 | config MTC_DIRECTORY |
| 130 | string "Directory where MTC firmware file is located" |
| 131 | default "." |
| 132 | help |
| 133 | Path to directory where MTC firmware file is located. |
| 134 | |
| 135 | config MTC_ADDRESS |
| 136 | hex |
| 137 | default 0x81000000 |
| 138 | help |
| 139 | The DRAM location where MTC firmware to be loaded in. This location |
| 140 | needs to be consistent with the location defined in tegra_mtc.ld |
| 141 | |
| 142 | endif # HAVE_MTC |
| 143 | |
Vladimir Serbinenko | 5226266 | 2015-10-11 02:17:21 +0200 | [diff] [blame] | 144 | endif # SOC_NVIDIA_TEGRA210 |