Angel Pons | c3f58f6 | 2020-04-05 15:46:41 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 5 | #include <soc/pci_devs.h> |
| 6 | #include <soc/ramstage.h> |
| 7 | #include <soc/sata.h> |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 8 | #include <console/console.h> |
| 9 | #include <delay.h> |
| 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ids.h> |
| 13 | |
| 14 | #include "chip.h" |
| 15 | |
| 16 | typedef struct soc_intel_baytrail_config config_t; |
| 17 | |
| 18 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 19 | { |
| 20 | pci_write_config32(dev, SATA_SIRI, idx); |
| 21 | pci_write_config32(dev, SATA_SIRD, value); |
| 22 | } |
| 23 | |
| 24 | static void sata_init(struct device *dev) |
| 25 | { |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 26 | config_t *config = config_of(dev); |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 27 | u32 reg32; |
| 28 | u16 reg16; |
| 29 | u8 reg8; |
| 30 | |
| 31 | printk(BIOS_DEBUG, "SATA: Initializing...\n"); |
| 32 | |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 33 | if (!config->sata_ahci) { |
| 34 | /* Set legacy or native decoding mode */ |
| 35 | if (config->ide_legacy_combined) { |
| 36 | reg8 = pci_read_config8(dev, 0x09); |
| 37 | reg8 &= ~0x5; |
| 38 | pci_write_config8(dev, 0x09, reg8); |
| 39 | } else { |
| 40 | reg8 = pci_read_config8(dev, 0x09); |
| 41 | reg8 |= 0x5; |
| 42 | pci_write_config8(dev, 0x09, reg8); |
| 43 | } |
| 44 | |
| 45 | /* Set capabilities pointer */ |
| 46 | pci_write_config8(dev, 0x34, 0x70); |
| 47 | reg16 = pci_read_config16(dev, 0x70); |
| 48 | reg16 &= ~0xFF00; |
| 49 | pci_write_config16(dev, 0x70, reg16); |
| 50 | } |
| 51 | |
| 52 | /* Primary timing - decode enable */ |
| 53 | reg16 = pci_read_config16(dev, 0x40); |
| 54 | reg16 |= 1 << 15; |
| 55 | pci_write_config16(dev, 0x40, reg16); |
| 56 | |
| 57 | /* Secondary timing - decode enable */ |
| 58 | reg16 = pci_read_config16(dev, 0x42); |
| 59 | reg16 |= 1 << 15; |
| 60 | pci_write_config16(dev, 0x42, reg16); |
| 61 | |
| 62 | /* Port mapping enables */ |
| 63 | reg16 = pci_read_config16(dev, 0x90); |
| 64 | reg16 |= (config->sata_port_map ^ 0x3) << 8; |
| 65 | pci_write_config16(dev, 0x90, reg16); |
| 66 | |
| 67 | /* Port control enables */ |
| 68 | reg16 = pci_read_config16(dev, 0x92); |
| 69 | reg16 &= ~0x003f; |
| 70 | reg16 |= config->sata_port_map; |
| 71 | pci_write_config16(dev, 0x92, reg16); |
| 72 | |
| 73 | if (config->sata_ahci) { |
Elyes HAOUAS | 0bc5d9d | 2022-01-27 07:55:34 +0100 | [diff] [blame] | 74 | u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 75 | |
| 76 | /* Enable CR memory space decoding */ |
| 77 | reg16 = pci_read_config16(dev, 0x04); |
| 78 | reg16 |= 0x2; |
| 79 | pci_write_config16(dev, 0x04, reg16); |
| 80 | |
| 81 | /* Set capability register */ |
| 82 | reg32 = read32(abar + 0x00); |
| 83 | reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM |
| 84 | reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits |
| 85 | reg32 |= (0x3 << 20); // Gen3 SATA |
| 86 | write32(abar + 0x00, reg32); |
| 87 | |
| 88 | /* Ports enabled */ |
| 89 | reg32 = read32(abar + 0x0c); |
| 90 | reg32 &= (u32)(~0x3f); |
| 91 | reg32 |= config->sata_port_map; |
| 92 | write32(abar + 0xc, reg32); |
| 93 | /* Two extra reads to latch */ |
| 94 | read32(abar + 0x0c); |
| 95 | read32(abar + 0x0c); |
| 96 | |
| 97 | /* Set cap2 - Support devslp */ |
| 98 | reg32 = (1 << 5) | (1 << 4) | (1 << 3); |
| 99 | write32(abar + 0x24, reg32); |
| 100 | |
| 101 | /* Set PxCMD registers */ |
| 102 | reg32 = read32(abar + 0x118); |
| 103 | reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | |
| 104 | (1 << 19) | (1 << 18) | (1 << 1)); |
| 105 | reg32 |= 2; |
| 106 | write32(abar + 0x118, reg32); |
| 107 | |
| 108 | reg32 = read32(abar + 0x198); |
| 109 | reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | |
| 110 | (1 << 19) | (1 << 18) | (1 << 1)); |
| 111 | reg32 |= 2; |
| 112 | write32(abar + 0x198, reg32); |
| 113 | |
| 114 | /* Clear reset features */ |
| 115 | write32(abar + 0xc8, 0); |
| 116 | |
| 117 | /* Enable interrupts */ |
| 118 | reg8 = read8(abar + 0x04); |
| 119 | reg8 |= 0x02; |
| 120 | write8(abar + 0x04, reg8); |
| 121 | |
| 122 | } else { |
| 123 | /* TODO(shawnn): Configure IDE SATA speed regs */ |
| 124 | } |
| 125 | |
| 126 | /* 1.4 us delay after configuring port / enable bits */ |
| 127 | udelay(2); |
| 128 | |
| 129 | /* Enable clock for ports */ |
| 130 | reg32 = pci_read_config32(dev, 0x94); |
Angel Pons | c3be055 | 2020-07-31 21:37:26 +0200 | [diff] [blame] | 131 | reg32 &= ~(config->sata_port_map << 24); |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 132 | pci_write_config32(dev, 0x94, reg32); |
| 133 | |
| 134 | /* Lock SataGc register */ |
| 135 | reg32 = (0x1 << 31) | (0x7 << 12); |
Angel Pons | c3be055 | 2020-07-31 21:37:26 +0200 | [diff] [blame] | 136 | pci_write_config32(dev, 0x9c, reg32); |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 137 | } |
| 138 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 139 | static void sata_enable(struct device *dev) |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 140 | { |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 141 | config_t *config = config_of(dev); |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 142 | u8 reg8; |
| 143 | u16 reg16; |
| 144 | u32 reg32; |
| 145 | |
| 146 | southcluster_enable_dev(dev); |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 147 | |
| 148 | /* Port mapping -- mask off SPD + SMS + SC bits, then re-set */ |
| 149 | reg16 = pci_read_config16(dev, 0x90); |
| 150 | reg16 &= ~0x03e0; |
| 151 | reg16 |= (config->sata_port_map ^ 0x3) << 8; |
Elyes HAOUAS | 4a83f1c | 2016-08-25 21:07:59 +0200 | [diff] [blame] | 152 | if (config->sata_ahci) |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 153 | reg16 |= 0x60; |
| 154 | pci_write_config16(dev, 0x90, reg16); |
| 155 | |
| 156 | /* Set reg 0x94 before starting configuration */ |
| 157 | reg32 = pci_read_config32(dev, 0x94); |
| 158 | reg32 &= (u32)(~0x1ff); |
| 159 | reg32 |= 0x183; |
| 160 | pci_write_config32(dev, 0x94, reg32); |
| 161 | |
| 162 | /* Set ORM bit */ |
| 163 | reg16 = pci_read_config16(dev, 0x92); |
| 164 | reg16 |= (1 << 15); |
| 165 | pci_write_config16(dev, 0x92, reg16); |
| 166 | |
| 167 | /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */ |
| 168 | reg32 = pci_read_config32(dev, 0x98); |
| 169 | reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5)); |
| 170 | reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) | |
| 171 | (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5); |
| 172 | pci_write_config32(dev, 0x98, reg32); |
| 173 | |
| 174 | /* CMD reg - set bus master enable (BME) */ |
| 175 | reg8 = pci_read_config8(dev, 0x04); |
| 176 | reg8 |= (1 << 2); |
| 177 | pci_write_config8(dev, 0x04, reg8); |
| 178 | |
| 179 | /* "Test mode registers" */ |
| 180 | sir_write(dev, 0x70, 0x00288301); |
| 181 | sir_write(dev, 0x54, 0x00000300); |
| 182 | sir_write(dev, 0x58, 0x50000000); |
| 183 | /* "OOB Detection Margin */ |
| 184 | sir_write(dev, 0x6c, 0x130C0603); |
| 185 | /* "Gasket Control" */ |
| 186 | sir_write(dev, 0xf4, 0); |
| 187 | |
| 188 | /* PCS - Enable requested SATA ports */ |
| 189 | reg8 = pci_read_config8(dev, 0x92); |
| 190 | reg8 &= ~0x03; |
| 191 | reg8 |= config->sata_port_map; |
| 192 | pci_write_config8(dev, 0x92, reg8); |
| 193 | } |
| 194 | |
| 195 | static struct device_operations sata_ops = { |
| 196 | .read_resources = pci_dev_read_resources, |
| 197 | .set_resources = pci_dev_set_resources, |
| 198 | .enable_resources = pci_dev_enable_resources, |
| 199 | .init = sata_init, |
| 200 | .enable = sata_enable, |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 201 | .ops_pci = &soc_pci_ops, |
| 202 | }; |
| 203 | |
| 204 | static const unsigned short pci_device_ids[] = { |
| 205 | IDE1_DEVID, IDE2_DEVID, /* IDE */ |
| 206 | AHCI1_DEVID, AHCI2_DEVID, /* AHCI */ |
| 207 | 0, |
| 208 | }; |
| 209 | |
| 210 | static const struct pci_driver baytrail_sata __pci_driver = { |
| 211 | .ops = &sata_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 212 | .vendor = PCI_VID_INTEL, |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 213 | .devices = pci_device_ids, |
| 214 | }; |