| Angel Pons | 796bd74 | 2019-01-04 00:28:19 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <stdint.h> |
| 15 | #include <string.h> |
| 16 | #include <arch/byteorder.h> |
| 17 | #include <arch/io.h> |
| 18 | #include <device/pci_def.h> |
| 19 | #include <device/pnp_def.h> |
| 20 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 21 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 22 | #include <southbridge/intel/bd82x6x/pch.h> |
| 23 | #include <cbfs.h> |
| 24 | |
| 25 | void pch_enable_lpc(void) |
| 26 | { |
| 27 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); |
| 28 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); |
| 29 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); |
| 30 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); |
| 31 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); |
| 32 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); |
| 33 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); |
| 34 | } |
| 35 | |
| 36 | void mainboard_rcba_config(void) |
| 37 | { |
| 38 | /* Disable devices. */ |
| 39 | RCBA32(0x3414) = 0x00000020; |
| 40 | } |
| 41 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 42 | { 1, 0, -1 }, |
| 43 | { 1, 0, -1 }, |
| 44 | { 1, 0, -1 }, |
| 45 | { 1, 0, -1 }, |
| 46 | { 1, 0, -1 }, |
| 47 | { 1, 0, -1 }, |
| 48 | { 1, 0, -1 }, |
| 49 | { 1, 0, -1 }, |
| 50 | { 1, 0, -1 }, |
| 51 | { 1, 0, -1 }, |
| 52 | { 1, 0, -1 }, |
| 53 | { 1, 0, -1 }, |
| 54 | { 1, 0, -1 }, |
| 55 | { 1, 0, -1 }, |
| 56 | }; |
| 57 | |
| 58 | void mainboard_early_init(int s3resume) |
| 59 | { |
| 60 | } |
| 61 | |
| 62 | void mainboard_config_superio(void) |
| 63 | { |
| 64 | } |
| 65 | |
| 66 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 67 | { |
| 68 | void *spd_file; |
| 69 | size_t spd_file_len = 0; |
| 70 | spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 71 | &spd_file_len); |
| 72 | if (spd_file && spd_file_len >= 1024) { |
| 73 | int i; |
| 74 | for (i = 0; i < 4; i++) |
| 75 | memcpy(&spd[i], spd_file + 256 * i, 128); |
| 76 | } |
| 77 | } |