Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014-2015 Intel Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Lee Leahy | 40c0543 | 2015-05-27 17:25:47 -0700 | [diff] [blame] | 17 | * Foundation, Inc. |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <cbmem.h> |
| 21 | #include <console/console.h> |
| 22 | #include <fsp_util.h> |
| 23 | #include <lib.h> /* hexdump */ |
| 24 | #include <reset.h> |
| 25 | #include <soc/intel/common/memmap.h> |
| 26 | #include <soc/pei_data.h> |
| 27 | #include <soc/romstage.h> |
| 28 | #include <string.h> |
| 29 | #include <timestamp.h> |
| 30 | |
| 31 | void raminit(struct romstage_params *params) |
| 32 | { |
| 33 | const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID; |
| 34 | EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root; |
| 35 | FSP_INFO_HEADER *fsp_header; |
| 36 | EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory; |
| 37 | FSP_MEMORY_INIT fsp_memory_init; |
| 38 | FSP_MEMORY_INIT_PARAMS fsp_memory_init_params; |
| 39 | const EFI_GUID fsp_reserved_guid = |
| 40 | FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID; |
| 41 | void *fsp_reserved_memory_area; |
| 42 | FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer; |
| 43 | void *hob_list_ptr; |
| 44 | FSP_SMBIOS_MEMORY_INFO *memory_info_hob; |
| 45 | const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID; |
| 46 | MEMORY_INIT_UPD memory_init_params; |
| 47 | const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; |
| 48 | u32 *mrc_hob; |
| 49 | u32 fsp_reserved_bytes; |
| 50 | MEMORY_INIT_UPD *original_params; |
| 51 | struct pei_data *pei_ptr; |
| 52 | EFI_STATUS status; |
| 53 | VPD_DATA_REGION *vpd_ptr; |
| 54 | UPD_DATA_REGION *upd_ptr; |
| 55 | int fsp_verification_failure = 0; |
| 56 | #if IS_ENABLED(CONFIG_DISPLAY_HOBS) |
| 57 | unsigned long int data; |
| 58 | EFI_PEI_HOB_POINTERS hob_ptr; |
| 59 | #endif |
| 60 | |
| 61 | /* |
| 62 | * Find and copy the UPD region to the stack so the platform can modify |
| 63 | * the settings if needed. Modifications to the UPD buffer are done in |
| 64 | * the platform callback code. The platform callback code is also |
| 65 | * responsible for assigning the UpdDataRngPtr to this buffer if any |
| 66 | * updates are made. The default state is to leave the UpdDataRngPtr |
| 67 | * set to NULL. This indicates that the FSP code will use the UPD |
| 68 | * region in the FSP binary. |
| 69 | */ |
| 70 | post_code(0x34); |
| 71 | fsp_header = params->chipset_context; |
| 72 | vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + |
| 73 | fsp_header->ImageBase); |
| 74 | printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr); |
| 75 | upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset + |
| 76 | fsp_header->ImageBase); |
| 77 | printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr); |
| 78 | original_params = (void *)((u8 *)upd_ptr + |
| 79 | upd_ptr->MemoryInitUpdOffset); |
| 80 | memcpy(&memory_init_params, original_params, |
| 81 | sizeof(memory_init_params)); |
| 82 | |
| 83 | /* Zero fill RT Buffer data and start populating fields. */ |
| 84 | memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer)); |
| 85 | pei_ptr = params->pei_data; |
| 86 | if (pei_ptr->boot_mode == SLEEP_STATE_S3) { |
| 87 | fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME; |
| 88 | } else if (pei_ptr->saved_data != NULL) { |
| 89 | fsp_rt_common_buffer.BootMode = |
| 90 | BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; |
| 91 | } else { |
| 92 | fsp_rt_common_buffer.BootMode = BOOT_WITH_FULL_CONFIGURATION; |
| 93 | } |
| 94 | fsp_rt_common_buffer.UpdDataRgnPtr = &memory_init_params; |
| 95 | fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size(); |
| 96 | |
| 97 | /* Get any board specific changes */ |
| 98 | fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data; |
| 99 | fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer; |
| 100 | fsp_memory_init_params.HobListPtr = &hob_list_ptr; |
| 101 | |
| 102 | /* Update the UPD data */ |
Duncan Laurie | 9dcd4f0 | 2015-08-17 18:09:14 -0700 | [diff] [blame] | 103 | soc_memory_init_params(params, &memory_init_params); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 104 | mainboard_memory_init_params(params, &memory_init_params); |
| 105 | post_code(0x36); |
| 106 | |
| 107 | /* Display the UPD data */ |
| 108 | if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) |
| 109 | soc_display_memory_init_params(original_params, |
| 110 | &memory_init_params); |
| 111 | |
| 112 | /* Call FspMemoryInit to initialize RAM */ |
| 113 | fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase |
| 114 | + fsp_header->FspMemoryInitEntryOffset); |
| 115 | printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init); |
| 116 | printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n", |
| 117 | fsp_memory_init_params.NvsBufferPtr); |
| 118 | printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n", |
| 119 | fsp_memory_init_params.RtBufferPtr); |
| 120 | printk(BIOS_SPEW, " 0x%p: HobListPtr\n", |
| 121 | fsp_memory_init_params.HobListPtr); |
| 122 | |
| 123 | timestamp_add_now(TS_FSP_MEMORY_INIT_START); |
| 124 | status = fsp_memory_init(&fsp_memory_init_params); |
| 125 | post_code(0x37); |
| 126 | timestamp_add_now(TS_FSP_MEMORY_INIT_END); |
| 127 | |
| 128 | printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); |
| 129 | if (status != EFI_SUCCESS) |
| 130 | die("ERROR - FspMemoryInit failed to initialize memory!\n"); |
| 131 | |
| 132 | /* Locate the FSP reserved memory area */ |
| 133 | fsp_reserved_bytes = 0; |
| 134 | fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr); |
| 135 | if (fsp_memory == NULL) { |
| 136 | fsp_verification_failure = 1; |
| 137 | printk(BIOS_DEBUG, |
| 138 | "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); |
| 139 | } else { |
| 140 | fsp_reserved_bytes = fsp_memory->ResourceLength; |
| 141 | printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n", |
| 142 | (unsigned long int)fsp_reserved_bytes); |
| 143 | } |
| 144 | |
| 145 | /* Display SMM area */ |
| 146 | #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) |
| 147 | char *smm_base; |
| 148 | size_t smm_size; |
| 149 | |
| 150 | smm_region((void **)&smm_base, &smm_size); |
| 151 | printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); |
| 152 | printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); |
| 153 | #endif |
| 154 | |
| 155 | /* Migrate CAR data */ |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 156 | printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); |
| 157 | if (pei_ptr->boot_mode != SLEEP_STATE_S3) { |
| 158 | cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 159 | fsp_reserved_bytes); |
| 160 | } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 161 | fsp_reserved_bytes)) { |
| 162 | #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) |
| 163 | printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); |
| 164 | /* Failed S3 resume, reset to come up cleanly */ |
| 165 | hard_reset(); |
| 166 | #endif |
| 167 | } |
| 168 | |
| 169 | /* Save the FSP runtime parameters. */ |
| 170 | fsp_set_runtime(params->chipset_context, hob_list_ptr); |
| 171 | |
| 172 | /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ |
| 173 | cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr); |
| 174 | if (cbmem_root == NULL) { |
| 175 | fsp_verification_failure = 1; |
| 176 | printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); |
| 177 | printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n", |
| 178 | fsp_rt_common_buffer.BootLoaderTolumSize); |
| 179 | } |
| 180 | |
| 181 | /* Locate the FSP_SMBIOS_MEMORY_INFO HOB */ |
| 182 | memory_info_hob = get_next_guid_hob(&memory_info_hob_guid, |
| 183 | hob_list_ptr); |
| 184 | if (NULL == memory_info_hob) { |
| 185 | printk(BIOS_ERR, "FSP_SMBIOS_MEMORY_INFO HOB missing!\n"); |
| 186 | fsp_verification_failure = 1; |
| 187 | } else { |
| 188 | printk(BIOS_DEBUG, |
| 189 | "FSP_SMBIOS_MEMORY_INFO HOB: 0x%p\n", |
| 190 | memory_info_hob); |
| 191 | } |
| 192 | |
| 193 | #if IS_ENABLED(CONFIG_DISPLAY_HOBS) |
| 194 | if (hob_list_ptr == NULL) |
| 195 | die("ERROR - HOB pointer is NULL!\n"); |
| 196 | |
| 197 | /* |
| 198 | * Verify that FSP is generating the required HOBs: |
| 199 | * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 |
| 200 | * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified above |
| 201 | * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified below |
| 202 | * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified above |
| 203 | * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit |
| 204 | * FSP_SMBIOS_MEMORY_INFO HOB verified above |
| 205 | */ |
| 206 | if (NULL != cbmem_root) { |
| 207 | printk(BIOS_DEBUG, |
| 208 | "7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n", |
| 209 | cbmem_root); |
| 210 | data = cbmem_root->PhysicalStart; |
| 211 | printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); |
| 212 | data = cbmem_root->ResourceLength; |
| 213 | printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); |
| 214 | } |
| 215 | hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr); |
| 216 | if (NULL == hob_ptr.Raw) { |
| 217 | printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); |
| 218 | fsp_verification_failure = |
| 219 | (params->pei_data->saved_data == NULL) ? 1 : 0; |
| 220 | } else { |
| 221 | printk(BIOS_DEBUG, |
| 222 | "7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n", |
| 223 | hob_ptr.Raw); |
| 224 | } |
| 225 | if (fsp_memory != NULL) { |
| 226 | printk(BIOS_DEBUG, |
| 227 | "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n", |
| 228 | fsp_memory); |
| 229 | data = fsp_memory->PhysicalStart; |
| 230 | printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); |
| 231 | data = fsp_memory->ResourceLength; |
| 232 | printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); |
| 233 | } |
| 234 | |
| 235 | /* Verify all the HOBs are present */ |
| 236 | if (fsp_verification_failure) |
| 237 | printk(BIOS_DEBUG, |
| 238 | "ERROR - Missing one or more required FSP HOBs!\n"); |
| 239 | |
| 240 | /* Display the HOBs */ |
| 241 | print_hob_type_structure(0, hob_list_ptr); |
| 242 | #endif |
| 243 | |
| 244 | /* Get the address of the CBMEM region for the FSP reserved memory */ |
| 245 | fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); |
| 246 | printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n", |
| 247 | fsp_reserved_memory_area); |
| 248 | |
| 249 | /* Verify the order of CBMEM root and FSP memory */ |
| 250 | if ((fsp_memory != NULL) && (cbmem_root != NULL) && |
| 251 | (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) { |
| 252 | fsp_verification_failure = 1; |
| 253 | printk(BIOS_DEBUG, |
| 254 | "ERROR - FSP reserved memory above CBMEM root!\n"); |
| 255 | } |
| 256 | |
| 257 | /* Verify that the FSP memory was properly reserved */ |
| 258 | if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) || |
| 259 | (fsp_memory->PhysicalStart != |
| 260 | (unsigned int)fsp_reserved_memory_area))) { |
| 261 | fsp_verification_failure = 1; |
| 262 | printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n"); |
| 263 | #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) |
| 264 | if (cbmem_root != NULL) { |
| 265 | size_t delta_bytes = (unsigned int)smm_base |
| 266 | - cbmem_root->PhysicalStart |
| 267 | - cbmem_root->ResourceLength; |
| 268 | printk(BIOS_DEBUG, |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 269 | "0x%08x: Chipset reserved bytes reported by FSP\n", |
| 270 | (unsigned int)delta_bytes); |
| 271 | die("Please verify the chipset reserved size\n"); |
| 272 | } |
| 273 | #endif |
| 274 | } |
| 275 | |
| 276 | /* Verify the FSP 1.1 HOB interface */ |
| 277 | if (fsp_verification_failure) |
| 278 | die("ERROR - Coreboot's requirements not met by FSP binary!\n"); |
| 279 | |
| 280 | /* Display the memory configuration */ |
| 281 | report_memory_config(); |
| 282 | |
| 283 | /* Locate the memory configuration data to speed up the next reboot */ |
| 284 | mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); |
| 285 | if (mrc_hob == NULL) |
| 286 | printk(BIOS_DEBUG, |
| 287 | "Memory Configuration Data Hob not present\n"); |
| 288 | else { |
| 289 | pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob); |
| 290 | pei_ptr->data_to_save_size = ALIGN( |
| 291 | ((u32)GET_HOB_LENGTH(mrc_hob)), 16); |
| 292 | } |
| 293 | } |
| 294 | |
| 295 | /* Initialize the UPD parameters for MemoryInit */ |
| 296 | __attribute__((weak)) void mainboard_memory_init_params( |
| 297 | struct romstage_params *params, |
| 298 | MEMORY_INIT_UPD *upd_ptr) |
| 299 | { |
| 300 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 301 | } |
| 302 | |
| 303 | /* Display the UPD parameters for MemoryInit */ |
| 304 | __attribute__((weak)) void soc_display_memory_init_params( |
| 305 | const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new) |
| 306 | { |
| 307 | printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); |
| 308 | hexdump32(BIOS_SPEW, new, sizeof(*new)); |
| 309 | } |
| 310 | |
| 311 | /* Initialize the UPD parameters for MemoryInit */ |
Duncan Laurie | 9dcd4f0 | 2015-08-17 18:09:14 -0700 | [diff] [blame] | 312 | __attribute__((weak)) void soc_memory_init_params( |
| 313 | struct romstage_params *params, |
| 314 | MEMORY_INIT_UPD *upd) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 315 | { |
| 316 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 317 | } |