Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
York Yang | 4a91f64 | 2014-11-25 15:54:08 -0700 | [diff] [blame] | 6 | * Copyright (C) 2014 Intel Corporation |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 22 | #include <baytrail/romstage.h> |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 23 | #include <drivers/intel/fsp/fsp_util.h> |
Martin Roth | 14ca52b | 2014-12-02 21:51:03 -0700 | [diff] [blame] | 24 | #include <pc80/mc146818rtc.h> |
| 25 | #include <console/console.h> |
Martin Roth | 9aadeb5 | 2014-12-14 14:12:11 -0700 | [diff] [blame] | 26 | #include <baytrail/gpio.h> |
York Yang | 4a91f64 | 2014-11-25 15:54:08 -0700 | [diff] [blame] | 27 | #include "chip.h" |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 28 | |
| 29 | /** |
| 30 | * /brief mainboard call for setup that needs to be done before fsp init |
| 31 | * |
| 32 | */ |
| 33 | void early_mainboard_romstage_entry() |
| 34 | { |
| 35 | |
| 36 | } |
| 37 | |
| 38 | /** |
| 39 | * Get function disables - most of these will be done automatically |
| 40 | * @param fd_mask |
| 41 | * @param fd2_mask |
| 42 | */ |
| 43 | void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) |
| 44 | { |
| 45 | |
| 46 | } |
| 47 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 48 | /** |
| 49 | * /brief mainboard call for setup that needs to be done after fsp init |
| 50 | * |
| 51 | */ |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 52 | void late_mainboard_romstage_entry() |
| 53 | { |
| 54 | |
| 55 | } |
| 56 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 57 | void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) |
| 58 | { |
| 59 | UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; |
Martin Roth | 14ca52b | 2014-12-02 21:51:03 -0700 | [diff] [blame] | 60 | u8 use_xhci = UpdData->PcdEnableXhci; |
Martin Roth | 9aadeb5 | 2014-12-14 14:12:11 -0700 | [diff] [blame] | 61 | u8 gpio5 = 0; |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 62 | |
York Yang | 4a91f64 | 2014-11-25 15:54:08 -0700 | [diff] [blame] | 63 | /* |
Martin Roth | 9aadeb5 | 2014-12-14 14:12:11 -0700 | [diff] [blame] | 64 | * Minnow Max Board |
| 65 | * Read SSUS gpio 5 to determine memory type |
| 66 | * 0 : 1GB SKU uses 2Gb density memory |
| 67 | * 1 : 2GB SKU uses 4Gb density memory |
York Yang | 4a91f64 | 2014-11-25 15:54:08 -0700 | [diff] [blame] | 68 | * |
Martin Roth | 9aadeb5 | 2014-12-14 14:12:11 -0700 | [diff] [blame] | 69 | * devicetree.cb assumes 1GB SKU board |
| 70 | */ |
| 71 | configure_ssus_gpio(5, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); |
| 72 | gpio5 = read_ssus_gpio(5); |
| 73 | if (gpio5) |
York Yang | 4a91f64 | 2014-11-25 15:54:08 -0700 | [diff] [blame] | 74 | UpdData->PcdMemoryParameters.DIMMDensity |
| 75 | += (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT); |
Martin Roth | 9aadeb5 | 2014-12-14 14:12:11 -0700 | [diff] [blame] | 76 | printk(BIOS_NOTICE, "%s GB Minnowboard Max detected.\n", |
| 77 | gpio5 ? "2 / 4" : "1" ); |
Martin Roth | 14ca52b | 2014-12-02 21:51:03 -0700 | [diff] [blame] | 78 | /* Update XHCI UPD value if required */ |
| 79 | get_option(&use_xhci, "use_xhci_over_ehci"); |
| 80 | if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) { |
| 81 | UpdData->PcdEnableXhci = use_xhci; |
| 82 | printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n", |
| 83 | UpdData->PcdEnableXhci?"Enabled":"Disabled"); |
| 84 | } |
| 85 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 86 | return; |
| 87 | } |