blob: a14472297a5690e8bf183713c55e563fda4c95c1 [file] [log] [blame]
Martin Rothe6df0412014-07-28 14:22:32 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC.
York Yang4a91f642014-11-25 15:54:08 -07006 * Copyright (C) 2014 Intel Corporation
Martin Rothe6df0412014-07-28 14:22:32 -06007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
Martin Rothe6df0412014-07-28 14:22:32 -060022#include <baytrail/romstage.h>
Martin Rothe6df0412014-07-28 14:22:32 -060023#include <drivers/intel/fsp/fsp_util.h>
Martin Roth14ca52b2014-12-02 21:51:03 -070024#include <pc80/mc146818rtc.h>
25#include <console/console.h>
York Yang4a91f642014-11-25 15:54:08 -070026#include "chip.h"
Martin Rothe6df0412014-07-28 14:22:32 -060027
28/**
29 * /brief mainboard call for setup that needs to be done before fsp init
30 *
31 */
32void early_mainboard_romstage_entry()
33{
34
35}
36
37/**
38 * Get function disables - most of these will be done automatically
39 * @param fd_mask
40 * @param fd2_mask
41 */
42void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
43{
44
45}
46
Martin Rothe6df0412014-07-28 14:22:32 -060047/**
48 * /brief mainboard call for setup that needs to be done after fsp init
49 *
50 */
Martin Rothe6df0412014-07-28 14:22:32 -060051void late_mainboard_romstage_entry()
52{
53
54}
55
Martin Rothe6df0412014-07-28 14:22:32 -060056void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
57{
58 UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
Martin Roth14ca52b2014-12-02 21:51:03 -070059 u8 use_xhci = UpdData->PcdEnableXhci;
Martin Rothe6df0412014-07-28 14:22:32 -060060
York Yang4a91f642014-11-25 15:54:08 -070061 /*
62 * Minnow Max Board : 1GB SKU uses 2Gb density memory
63 * 2GB SKU uses 4Gb densiry memory
64 *
65 * devicetree.cb assume 1GB SKU board
66 */
67 if (CONFIG_MINNOWMAX_2GB_SKU)
68 UpdData->PcdMemoryParameters.DIMMDensity
69 += (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT);
Martin Rothe6df0412014-07-28 14:22:32 -060070
Martin Roth14ca52b2014-12-02 21:51:03 -070071 /* Update XHCI UPD value if required */
72 get_option(&use_xhci, "use_xhci_over_ehci");
73 if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {
74 UpdData->PcdEnableXhci = use_xhci;
75 printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n",
76 UpdData->PcdEnableXhci?"Enabled":"Disabled");
77 }
78
Martin Rothe6df0412014-07-28 14:22:32 -060079 return;
80}