Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
York Yang | 4a91f64 | 2014-11-25 15:54:08 -0700 | [diff] [blame] | 6 | * Copyright (C) 2014 Intel Corporation |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 22 | #include <baytrail/romstage.h> |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 23 | #include <drivers/intel/fsp/fsp_util.h> |
Martin Roth | 14ca52b | 2014-12-02 21:51:03 -0700 | [diff] [blame^] | 24 | #include <pc80/mc146818rtc.h> |
| 25 | #include <console/console.h> |
York Yang | 4a91f64 | 2014-11-25 15:54:08 -0700 | [diff] [blame] | 26 | #include "chip.h" |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 27 | |
| 28 | /** |
| 29 | * /brief mainboard call for setup that needs to be done before fsp init |
| 30 | * |
| 31 | */ |
| 32 | void early_mainboard_romstage_entry() |
| 33 | { |
| 34 | |
| 35 | } |
| 36 | |
| 37 | /** |
| 38 | * Get function disables - most of these will be done automatically |
| 39 | * @param fd_mask |
| 40 | * @param fd2_mask |
| 41 | */ |
| 42 | void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) |
| 43 | { |
| 44 | |
| 45 | } |
| 46 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 47 | /** |
| 48 | * /brief mainboard call for setup that needs to be done after fsp init |
| 49 | * |
| 50 | */ |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 51 | void late_mainboard_romstage_entry() |
| 52 | { |
| 53 | |
| 54 | } |
| 55 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 56 | void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) |
| 57 | { |
| 58 | UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; |
Martin Roth | 14ca52b | 2014-12-02 21:51:03 -0700 | [diff] [blame^] | 59 | u8 use_xhci = UpdData->PcdEnableXhci; |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 60 | |
York Yang | 4a91f64 | 2014-11-25 15:54:08 -0700 | [diff] [blame] | 61 | /* |
| 62 | * Minnow Max Board : 1GB SKU uses 2Gb density memory |
| 63 | * 2GB SKU uses 4Gb densiry memory |
| 64 | * |
| 65 | * devicetree.cb assume 1GB SKU board |
| 66 | */ |
| 67 | if (CONFIG_MINNOWMAX_2GB_SKU) |
| 68 | UpdData->PcdMemoryParameters.DIMMDensity |
| 69 | += (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT); |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 70 | |
Martin Roth | 14ca52b | 2014-12-02 21:51:03 -0700 | [diff] [blame^] | 71 | /* Update XHCI UPD value if required */ |
| 72 | get_option(&use_xhci, "use_xhci_over_ehci"); |
| 73 | if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) { |
| 74 | UpdData->PcdEnableXhci = use_xhci; |
| 75 | printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n", |
| 76 | UpdData->PcdEnableXhci?"Enabled":"Disabled"); |
| 77 | } |
| 78 | |
Martin Roth | e6df041 | 2014-07-28 14:22:32 -0600 | [diff] [blame] | 79 | return; |
| 80 | } |