Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | d0310fa | 2019-10-02 00:21:01 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/pci_ops.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
| 7 | #include <device/pci_def.h> |
| 8 | #include "pch.h" |
| 9 | |
| 10 | /* Set bit in function disable register to hide this device */ |
| 11 | static void pch_disable_devfn(struct device *dev) |
| 12 | { |
| 13 | switch (dev->path.pci.devfn) { |
| 14 | case PCI_DEVFN(22, 0): /* MEI #1 */ |
| 15 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 16 | break; |
| 17 | case PCI_DEVFN(22, 1): /* MEI #2 */ |
| 18 | RCBA32_OR(FD2, PCH_DISABLE_MEI2); |
| 19 | break; |
| 20 | case PCI_DEVFN(22, 2): /* IDE-R */ |
| 21 | RCBA32_OR(FD2, PCH_DISABLE_IDER); |
| 22 | break; |
| 23 | case PCI_DEVFN(22, 3): /* KT */ |
| 24 | RCBA32_OR(FD2, PCH_DISABLE_KT); |
| 25 | break; |
| 26 | case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ |
| 27 | RCBA32_OR(BUC, PCH_DISABLE_GBE); |
| 28 | break; |
| 29 | case PCI_DEVFN(26, 0): /* EHCI #2 */ |
| 30 | RCBA32_OR(FD, PCH_DISABLE_EHCI2); |
| 31 | break; |
| 32 | case PCI_DEVFN(27, 0): /* HD Audio Controller */ |
| 33 | RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); |
| 34 | break; |
| 35 | case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ |
| 36 | case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ |
| 37 | case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ |
| 38 | case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ |
| 39 | case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ |
| 40 | case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ |
| 41 | case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ |
| 42 | case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ |
| 43 | RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); |
| 44 | break; |
| 45 | case PCI_DEVFN(29, 0): /* EHCI #1 */ |
| 46 | RCBA32_OR(FD, PCH_DISABLE_EHCI1); |
| 47 | break; |
| 48 | case PCI_DEVFN(31, 0): /* LPC */ |
| 49 | RCBA32_OR(FD, PCH_DISABLE_LPC); |
| 50 | break; |
| 51 | case PCI_DEVFN(31, 2): /* SATA #1 */ |
| 52 | RCBA32_OR(FD, PCH_DISABLE_SATA1); |
| 53 | break; |
| 54 | case PCI_DEVFN(31, 3): /* SMBUS */ |
| 55 | RCBA32_OR(FD, PCH_DISABLE_SMBUS); |
| 56 | break; |
| 57 | case PCI_DEVFN(31, 5): /* SATA #22 */ |
| 58 | RCBA32_OR(FD, PCH_DISABLE_SATA2); |
| 59 | break; |
| 60 | case PCI_DEVFN(31, 6): /* Thermal Subsystem */ |
| 61 | RCBA32_OR(FD, PCH_DISABLE_THERMAL); |
| 62 | break; |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | void pch_enable(struct device *dev) |
| 67 | { |
Elyes HAOUAS | 8b6dfde | 2020-04-28 09:58:21 +0200 | [diff] [blame] | 68 | u16 reg16; |
Arthur Heymans | d0310fa | 2019-10-02 00:21:01 +0200 | [diff] [blame] | 69 | |
| 70 | if (!dev->enabled) { |
| 71 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 72 | |
| 73 | /* Ensure memory, io, and bus master are all disabled */ |
Elyes HAOUAS | 8b6dfde | 2020-04-28 09:58:21 +0200 | [diff] [blame] | 74 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 75 | reg16 &= ~(PCI_COMMAND_MASTER | |
Arthur Heymans | d0310fa | 2019-10-02 00:21:01 +0200 | [diff] [blame] | 76 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Elyes HAOUAS | 8b6dfde | 2020-04-28 09:58:21 +0200 | [diff] [blame] | 77 | pci_write_config16(dev, PCI_COMMAND, reg16); |
Arthur Heymans | d0310fa | 2019-10-02 00:21:01 +0200 | [diff] [blame] | 78 | |
| 79 | /* Disable this device if possible */ |
| 80 | pch_disable_devfn(dev); |
| 81 | } else { |
| 82 | /* Enable SERR */ |
Elyes HAOUAS | 8b6dfde | 2020-04-28 09:58:21 +0200 | [diff] [blame] | 83 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); |
Arthur Heymans | d0310fa | 2019-10-02 00:21:01 +0200 | [diff] [blame] | 84 | } |
| 85 | } |
| 86 | |
| 87 | struct chip_operations southbridge_intel_ibexpeak_ops = { |
| 88 | CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge") |
| 89 | .enable_dev = pch_enable, |
| 90 | }; |