blob: 275ed3d6fa4dadf5468400731cbe1ac83de0e7dc [file] [log] [blame]
Siyuan Wang3e32cc02013-07-09 17:16:20 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010017 * Foundation, Inc.
Siyuan Wang3e32cc02013-07-09 17:16:20 +080018 */
19
20#include <console/console.h>
21#include <arch/io.h>
Kyösti Mälkki8ae16a42014-06-19 20:44:34 +030022#include <arch/acpi.h>
Vladimir Serbinenkodb09b0622014-10-08 22:15:17 +020023#include <arch/acpigen.h>
Siyuan Wang3e32cc02013-07-09 17:16:20 +080024#include <stdint.h>
25#include <device/device.h>
26#include <device/pci.h>
27#include <device/pci_ids.h>
28#include <device/hypertransport.h>
29#include <stdlib.h>
30#include <string.h>
31#include <lib.h>
32#include <cpu/cpu.h>
33#include <cbmem.h>
34
35#include <cpu/x86/lapic.h>
36#include <cpu/amd/mtrr.h>
37
38#include <Porting.h>
39#include <AGESA.h>
40#include <Options.h>
41#include <Topology.h>
42#include <cpu/amd/amdfam16.h>
43#include <cpuRegisters.h>
Kyösti Mälkkif21c2ac2014-10-19 09:35:18 +030044#include <northbridge/amd/agesa/agesawrapper.h>
Siyuan Wang3e32cc02013-07-09 17:16:20 +080045
46#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
47
Siyuan Wang3e32cc02013-07-09 17:16:20 +080048typedef struct dram_base_mask {
49 u32 base; //[47:27] at [28:8]
50 u32 mask; //[47:27] at [28:8] and enable at bit 0
51} dram_base_mask_t;
52
53static unsigned node_nums;
54static unsigned sblink;
55static device_t __f0_dev[MAX_NODE_NUMS];
56static device_t __f1_dev[MAX_NODE_NUMS];
57static device_t __f2_dev[MAX_NODE_NUMS];
58static device_t __f4_dev[MAX_NODE_NUMS];
59static unsigned fx_devs = 0;
60
61static dram_base_mask_t get_dram_base_mask(u32 nodeid)
62{
63 device_t dev;
64 dram_base_mask_t d;
65 dev = __f1_dev[0];
66 u32 temp;
67 temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
68 d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
69 temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
70 d.mask |= temp<<21;
71 temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
72 d.mask |= (temp & 1); // enable bit
73 d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
74 temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
75 d.base |= temp<<21;
76 return d;
77}
78
79static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
80 u32 io_min, u32 io_max)
81{
82 u32 i;
83 u32 tempreg;
84 /* io range allocation */
85 tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
86 for (i=0; i<node_nums; i++)
87 pci_write_config32(__f1_dev[i], reg+4, tempreg);
88 tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
89#if 0
90 // FIXME: can we use VGA reg instead?
91 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
92 printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
93 __func__, dev_path(dev), link);
94 tempreg |= PCI_IO_BASE_VGA_EN;
95 }
96 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
97 tempreg |= PCI_IO_BASE_NO_ISA;
98 }
99#endif
100 for (i=0; i<node_nums; i++)
101 pci_write_config32(__f1_dev[i], reg, tempreg);
102}
103
104static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
105{
106 u32 i;
107 u32 tempreg;
108 /* io range allocation */
109 tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
110 for (i=0; i<nodes; i++)
111 pci_write_config32(__f1_dev[i], reg+4, tempreg);
112 tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
113 for (i=0; i<node_nums; i++)
114 pci_write_config32(__f1_dev[i], reg, tempreg);
115}
116
117static device_t get_node_pci(u32 nodeid, u32 fn)
118{
119#if MAX_NODE_NUMS + CONFIG_CDB >= 32
120 if ((CONFIG_CDB + nodeid) < 32) {
121 return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
122 } else {
123 return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
124 }
125#else
126 return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
127#endif
128}
129
130static void get_fx_devs(void)
131{
132 int i;
133 for (i = 0; i < MAX_NODE_NUMS; i++) {
134 __f0_dev[i] = get_node_pci(i, 0);
135 __f1_dev[i] = get_node_pci(i, 1);
136 __f2_dev[i] = get_node_pci(i, 2);
137 __f4_dev[i] = get_node_pci(i, 4);
138 if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
139 fx_devs = i+1;
140 }
141 if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
142 die("Cannot find 0:0x18.[0|1]\n");
143 }
144 printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
145}
146
147static u32 f1_read_config32(unsigned reg)
148{
149 if (fx_devs == 0)
150 get_fx_devs();
151 return pci_read_config32(__f1_dev[0], reg);
152}
153
154static void f1_write_config32(unsigned reg, u32 value)
155{
156 int i;
157 if (fx_devs == 0)
158 get_fx_devs();
159 for(i = 0; i < fx_devs; i++) {
160 device_t dev;
161 dev = __f1_dev[i];
162 if (dev && dev->enabled) {
163 pci_write_config32(dev, reg, value);
164 }
165 }
166}
167
168static u32 amdfam16_nodeid(device_t dev)
169{
170#if MAX_NODE_NUMS == 64
171 unsigned busn;
172 busn = dev->bus->secondary;
173 if (busn != CONFIG_CBB) {
174 return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
175 } else {
176 return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
177 }
178
179#else
180 return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
181#endif
182}
183
184static void set_vga_enable_reg(u32 nodeid, u32 linkn)
185{
186 u32 val;
187
188 val = 1 | (nodeid<<4) | (linkn<<12);
189 /* it will routing
190 * (1)mmio 0xa0000:0xbffff
191 * (2)io 0x3b0:0x3bb, 0x3c0:0x3df
192 */
193 f1_write_config32(0xf4, val);
194
195}
196
197/**
198 * @return
199 * @retval 2 resoure does not exist, usable
200 * @retval 0 resource exists, not usable
201 * @retval 1 resource exist, resource has been allocated before
202 */
203static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
204 unsigned goal_link)
205{
206 struct resource *res;
207 unsigned nodeid, link = 0;
208 int result;
209 res = 0;
210 for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
211 device_t dev;
212 dev = __f0_dev[nodeid];
213 if (!dev)
214 continue;
215 for (link = 0; !res && (link < 8); link++) {
216 res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
217 }
218 }
219 result = 2;
220 if (res) {
221 result = 0;
222 if ((goal_link == (link - 1)) &&
223 (goal_nodeid == (nodeid - 1)) &&
224 (res->flags <= 1)) {
225 result = 1;
226 }
227 }
228 return result;
229}
230
231static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link)
232{
233 struct resource *resource;
234 u32 free_reg, reg;
235 resource = 0;
236 free_reg = 0;
237 for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
238 int result;
239 result = reg_useable(reg, dev, nodeid, link);
240 if (result == 1) {
241 /* I have been allocated this one */
242 break;
243 }
244 else if (result > 1) {
245 /* I have a free register pair */
246 free_reg = reg;
247 }
248 }
249 if (reg > 0xd8) {
250 reg = free_reg; // if no free, the free_reg still be 0
251 }
252
253 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
254
255 return resource;
256}
257
258static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link)
259{
260 struct resource *resource;
261 u32 free_reg, reg;
262 resource = 0;
263 free_reg = 0;
264 for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
265 int result;
266 result = reg_useable(reg, dev, nodeid, link);
267 if (result == 1) {
268 /* I have been allocated this one */
269 break;
270 }
271 else if (result > 1) {
272 /* I have a free register pair */
273 free_reg = reg;
274 }
275 }
276 if (reg > 0xb8) {
277 reg = free_reg;
278 }
279
280 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
281 return resource;
282}
283
284static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link)
285{
286 struct resource *resource;
287
288 /* Initialize the io space constraints on the current bus */
289 resource = amdfam16_find_iopair(dev, nodeid, link);
290 if (resource) {
291 u32 align;
292 align = log2(HT_IO_HOST_ALIGN);
293 resource->base = 0;
294 resource->size = 0;
295 resource->align = align;
296 resource->gran = align;
297 resource->limit = 0xffffUL;
298 resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
299 }
300
301 /* Initialize the prefetchable memory constraints on the current bus */
302 resource = amdfam16_find_mempair(dev, nodeid, link);
303 if (resource) {
304 resource->base = 0;
305 resource->size = 0;
306 resource->align = log2(HT_MEM_HOST_ALIGN);
307 resource->gran = log2(HT_MEM_HOST_ALIGN);
308 resource->limit = 0xffffffffffULL;
309 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
310 resource->flags |= IORESOURCE_BRIDGE;
311 }
312
313 /* Initialize the memory constraints on the current bus */
314 resource = amdfam16_find_mempair(dev, nodeid, link);
315 if (resource) {
316 resource->base = 0;
317 resource->size = 0;
318 resource->align = log2(HT_MEM_HOST_ALIGN);
319 resource->gran = log2(HT_MEM_HOST_ALIGN);
320 resource->limit = 0xffffffffffULL;
321 resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
322 }
323
324}
325
326static void read_resources(device_t dev)
327{
328 u32 nodeid;
329 struct bus *link;
330
331 nodeid = amdfam16_nodeid(dev);
332 for (link = dev->link_list; link; link = link->next) {
333 if (link->children) {
334 amdfam16_link_read_bases(dev, nodeid, link->link_num);
335 }
336 }
Edward O'Callaghan66c65322014-11-21 01:43:38 +1100337
338 /*
339 * This MMCONF resource must be reserved in the PCI_DOMAIN.
340 * It is not honored by the coreboot resource allocator if it is in
341 * the APIC_CLUSTER.
342 */
343#if CONFIG_MMCONF_SUPPORT
344 struct resource *resource = new_resource(dev, 0xc0010058);
345 resource->base = CONFIG_MMCONF_BASE_ADDRESS;
346 resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
347 resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
348 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
349#endif
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800350}
351
352static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
353{
354 resource_t rbase, rend;
355 unsigned reg, link_num;
356 char buf[50];
357
358 /* Make certain the resource has actually been set */
359 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
360 return;
361 }
362
363 /* If I have already stored this resource don't worry about it */
364 if (resource->flags & IORESOURCE_STORED) {
365 return;
366 }
367
368 /* Only handle PCI memory and IO resources */
369 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
370 return;
371
372 /* Ensure I am actually looking at a resource of function 1 */
373 if ((resource->index & 0xffff) < 0x1000) {
374 return;
375 }
376 /* Get the base address */
377 rbase = resource->base;
378
379 /* Get the limit (rounded up) */
380 rend = resource_end(resource);
381
382 /* Get the register and link */
383 reg = resource->index & 0xfff; // 4k
384 link_num = IOINDEX_LINK(resource->index);
385
386 if (resource->flags & IORESOURCE_IO) {
387 set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
388 }
389 else if (resource->flags & IORESOURCE_MEM) {
Edward O'Callaghanae5fd342014-11-20 19:58:09 +1100390 set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8]
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800391 }
392 resource->flags |= IORESOURCE_STORED;
Vladimir Serbinenkoa37383d2013-11-26 02:41:26 +0100393 snprintf(buf, sizeof (buf), " <node %x link %x>",
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800394 nodeid, link_num);
395 report_resource_stored(dev, resource, buf);
396}
397
398/**
399 * I tried to reuse the resource allocation code in set_resource()
400 * but it is too difficult to deal with the resource allocation magic.
401 */
402
403static void create_vga_resource(device_t dev, unsigned nodeid)
404{
405 struct bus *link;
406
407 /* find out which link the VGA card is connected,
408 * we only deal with the 'first' vga card */
409 for (link = dev->link_list; link; link = link->next) {
410 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
411#if CONFIG_MULTIPLE_VGA_ADAPTERS
412 extern device_t vga_pri; // the primary vga device, defined in device.c
413 printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
414 link->secondary,link->subordinate);
415 /* We need to make sure the vga_pri is under the link */
416 if((vga_pri->bus->secondary >= link->secondary ) &&
417 (vga_pri->bus->secondary <= link->subordinate )
418 )
419#endif
420 break;
421 }
422 }
423
424 /* no VGA card installed */
425 if (link == NULL)
426 return;
427
428 printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink);
429 set_vga_enable_reg(nodeid, sblink);
430}
431
432static void set_resources(device_t dev)
433{
434 unsigned nodeid;
435 struct bus *bus;
436 struct resource *res;
437
438 /* Find the nodeid */
439 nodeid = amdfam16_nodeid(dev);
440
441 create_vga_resource(dev, nodeid); //TODO: do we need this?
442
443 /* Set each resource we have found */
444 for (res = dev->resource_list; res; res = res->next) {
445 set_resource(dev, res, nodeid);
446 }
447
448 for (bus = dev->link_list; bus; bus = bus->next) {
449 if (bus->children) {
450 assign_resources(bus);
451 }
452 }
Edward O'Callaghan66c65322014-11-21 01:43:38 +1100453
454 /* Print the MMCONF region if it has been reserved. */
455 res = find_resource(dev, 0xc0010058);
456 if (res) {
457 report_resource_stored(dev, res, " <mmconfig>");
458 }
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800459}
460
Vladimir Serbinenkodb09b0622014-10-08 22:15:17 +0200461
Vladimir Serbinenko807127f2014-11-09 13:36:18 +0100462static unsigned long acpi_fill_hest(acpi_hest_t *hest)
Vladimir Serbinenkodb09b0622014-10-08 22:15:17 +0200463{
464 void *addr, *current;
465
466 /* Skip the HEST header. */
467 current = (void *)(hest + 1);
468
469 addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
470 if (addr != NULL)
471 current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
472
473 addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
474 if (addr != NULL)
475 current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
476
477 return (unsigned long)current;
478}
479
Alexander Couzens5eea4582015-04-12 22:18:55 +0200480static void northbridge_fill_ssdt_generator(device_t device)
Vladimir Serbinenkodb09b0622014-10-08 22:15:17 +0200481{
482 msr_t msr;
483 char pscope[] = "\\_SB.PCI0";
484
485 acpigen_write_scope(pscope);
486 msr = rdmsr(TOP_MEM);
487 acpigen_write_name_dword("TOM1", msr.lo);
488 msr = rdmsr(TOP_MEM2);
489 /*
490 * Since XP only implements parts of ACPI 2.0, we can't use a qword
491 * here.
492 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
493 * slide 22ff.
494 * Shift value right by 20 bit to make it fit into 32bit,
495 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
496 */
497 acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
498 acpigen_pop_len();
499}
500
Alexander Couzens83fc32f2015-04-12 22:28:37 +0200501static unsigned long agesa_write_acpi_tables(device_t device,
502 unsigned long current,
Vladimir Serbinenkodb09b0622014-10-08 22:15:17 +0200503 acpi_rsdp_t *rsdp)
504{
505 acpi_srat_t *srat;
506 acpi_slit_t *slit;
507 acpi_header_t *ssdt;
508 acpi_header_t *alib;
509 acpi_header_t *ivrs;
510 acpi_hest_t *hest;
511
512 /* HEST */
513 current = ALIGN(current, 8);
514 hest = (acpi_hest_t *)current;
Vladimir Serbinenko807127f2014-11-09 13:36:18 +0100515 acpi_write_hest((void *)current, acpi_fill_hest);
Vladimir Serbinenkodb09b0622014-10-08 22:15:17 +0200516 acpi_add_table(rsdp, (void *)current);
517 current += ((acpi_header_t *)current)->length;
518
519 current = ALIGN(current, 8);
520 printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
521 ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
522 if (ivrs != NULL) {
523 memcpy((void *)current, ivrs, ivrs->length);
524 ivrs = (acpi_header_t *) current;
525 current += ivrs->length;
526 acpi_add_table(rsdp, ivrs);
527 } else {
528 printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
529 }
530
531 /* SRAT */
532 current = ALIGN(current, 8);
533 printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
534 srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
535 if (srat != NULL) {
536 memcpy((void *)current, srat, srat->header.length);
537 srat = (acpi_srat_t *) current;
538 current += srat->header.length;
539 acpi_add_table(rsdp, srat);
540 } else {
541 printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
542 }
543
544 /* SLIT */
545 current = ALIGN(current, 8);
546 printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
547 slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
548 if (slit != NULL) {
549 memcpy((void *)current, slit, slit->header.length);
550 slit = (acpi_slit_t *) current;
551 current += slit->header.length;
552 acpi_add_table(rsdp, slit);
553 } else {
554 printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
555 }
556
557 /* ALIB */
558 current = ALIGN(current, 16);
559 printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
560 alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
561 if (alib != NULL) {
562 memcpy((void *)current, alib, alib->length);
563 alib = (acpi_header_t *) current;
564 current += alib->length;
565 acpi_add_table(rsdp, (void *)alib);
566 }
567 else {
568 printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
569 }
570
571 /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */
572 /* SSDT */
573 current = ALIGN(current, 16);
574 printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
575 ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
576 if (ssdt != NULL) {
577 memcpy((void *)current, ssdt, ssdt->length);
578 ssdt = (acpi_header_t *) current;
579 current += ssdt->length;
580 }
581 else {
582 printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
583 }
584 acpi_add_table(rsdp,ssdt);
585
586 printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
587
588 return current;
589}
590
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800591static struct device_operations northbridge_operations = {
592 .read_resources = read_resources,
593 .set_resources = set_resources,
594 .enable_resources = pci_dev_enable_resources,
Edward O'Callaghand994ef12014-11-21 02:22:33 +1100595 .init = DEVICE_NOOP,
Vladimir Serbinenkodb09b0622014-10-08 22:15:17 +0200596 .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator,
597 .write_acpi_tables = agesa_write_acpi_tables,
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800598 .enable = 0,
599 .ops_pci = 0,
600};
601
602static const struct pci_driver family16_northbridge __pci_driver = {
603 .ops = &northbridge_operations,
604 .vendor = PCI_VENDOR_ID_AMD,
605 .device = PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT,
606};
607
608static const struct pci_driver family10_northbridge __pci_driver = {
609 .ops = &northbridge_operations,
610 .vendor = PCI_VENDOR_ID_AMD,
611 .device = PCI_DEVICE_ID_AMD_10H_NB_HT,
612};
613
Kyösti Mälkki4ee82c62014-11-25 16:03:12 +0200614static void fam16_finalize(void *chip_info)
615{
616 device_t dev;
617 u32 value;
618 dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
619 pci_write_config32(dev, 0xF8, 0);
620 pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
621
622 /* disable No Snoop */
623 dev = dev_find_slot(0, PCI_DEVFN(1, 1));
624 value = pci_read_config32(dev, 0x60);
625 value &= ~(1 << 11);
626 pci_write_config32(dev, 0x60, value);
627}
628
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800629struct chip_operations northbridge_amd_agesa_family16kb_ops = {
630 CHIP_NAME("AMD FAM16 Northbridge")
631 .enable_dev = 0,
Kyösti Mälkki4ee82c62014-11-25 16:03:12 +0200632 .final = fam16_finalize,
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800633};
634
635static void domain_read_resources(device_t dev)
636{
637 unsigned reg;
638
639 /* Find the already assigned resource pairs */
640 get_fx_devs();
641 for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
642 u32 base, limit;
643 base = f1_read_config32(reg);
644 limit = f1_read_config32(reg + 0x04);
645 /* Is this register allocated? */
646 if ((base & 3) != 0) {
647 unsigned nodeid, reg_link;
648 device_t reg_dev;
649 if (reg<0xc0) { // mmio
650 nodeid = (limit & 0xf) + (base&0x30);
651 } else { // io
652 nodeid = (limit & 0xf) + ((base>>4)&0x30);
653 }
654 reg_link = (limit >> 4) & 7;
655 reg_dev = __f0_dev[nodeid];
656 if (reg_dev) {
657 /* Reserve the resource */
658 struct resource *res;
659 res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
660 if (res) {
661 res->flags = 1;
662 }
663 }
664 }
665 }
666 /* FIXME: do we need to check extend conf space?
667 I don't believe that much preset value */
668
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800669 pci_domain_read_resources(dev);
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800670}
671
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800672static void domain_enable_resources(device_t dev)
673{
Kyösti Mälkki8ae16a42014-06-19 20:44:34 +0300674 if (acpi_is_wakeup_s3())
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300675 agesawrapper_fchs3laterestore();
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800676
677 /* Must be called after PCI enumeration and resource allocation */
Kyösti Mälkkib139b5e2014-10-20 07:41:20 +0300678 if (!acpi_is_wakeup_s3()) {
679 /* Enable MMIO on AMD CPU Address Map Controller */
Kyösti Mälkki48518f02014-11-25 14:20:57 +0200680 amd_initcpuio();
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800681
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300682 agesawrapper_amdinitmid();
Kyösti Mälkkib139b5e2014-10-20 07:41:20 +0300683 }
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800684 printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
685}
686
687#if CONFIG_HW_MEM_HOLE_SIZEK != 0
688struct hw_mem_hole_info {
689 unsigned hole_startk;
690 int node_id;
691};
692static struct hw_mem_hole_info get_hw_mem_hole_info(void)
693{
694 struct hw_mem_hole_info mem_hole;
695 int i;
696 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
697 mem_hole.node_id = -1;
698 for (i = 0; i < node_nums; i++) {
699 dram_base_mask_t d;
700 u32 hole;
701 d = get_dram_base_mask(i);
702 if (!(d.mask & 1)) continue; // no memory on this node
703 hole = pci_read_config32(__f1_dev[i], 0xf0);
704 if (hole & 2) { // we find the hole
705 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
706 mem_hole.node_id = i; // record the node No with hole
707 break; // only one hole
708 }
709 }
Kyösti Mälkki2f9b3af2014-06-26 05:30:54 +0300710
711 /* We need to double check if there is special set on base reg and limit reg
712 * are not continuous instead of hole, it will find out its hole_startk.
713 */
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800714 if (mem_hole.node_id == -1) {
715 resource_t limitk_pri = 0;
716 for (i=0; i<node_nums; i++) {
717 dram_base_mask_t d;
718 resource_t base_k, limit_k;
719 d = get_dram_base_mask(i);
720 if (!(d.base & 1)) continue;
721 base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
722 if (base_k > 4 *1024 * 1024) break; // don't need to go to check
723 if (limitk_pri != base_k) { // we find the hole
724 mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
725 mem_hole.node_id = i;
726 break; //only one hole
727 }
728 limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
729 limitk_pri = limit_k;
730 }
731 }
732 return mem_hole;
733}
734#endif
735
736#define ONE_MB_SHIFT 20
737
738static void setup_uma_memory(void)
739{
740#if CONFIG_GFXUMA
741 uint32_t topmem = (uint32_t) bsp_topmem();
742 uint32_t sys_mem;
743
744 /* refer to UMA Size Consideration in Family16h BKDG. */
745 /* Please reference MemNGetUmaSizeOR () */
746 /*
747 * Total system memory UMASize
748 * >= 2G 512M
749 * >=1G 256M
750 * <1G 64M
751 */
752 sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size
753 if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) {
754 uma_memory_size = 512 << ONE_MB_SHIFT;
755 } else if (sys_mem >= 1024 << ONE_MB_SHIFT) {
756 uma_memory_size = 256 << ONE_MB_SHIFT;
757 } else {
758 uma_memory_size = 64 << ONE_MB_SHIFT;
759 }
760 uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
761
762 printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
763 __func__, uma_memory_size, uma_memory_base);
764
765 /* TODO: TOP_MEM2 */
766#endif
767}
768
769
770static void domain_set_resources(device_t dev)
771{
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800772 unsigned long mmio_basek;
773 u32 pci_tolm;
Kyösti Mälkki2b790f62013-09-03 05:25:57 +0300774 u64 ramtop = 0;
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800775 int i, idx;
776 struct bus *link;
777#if CONFIG_HW_MEM_HOLE_SIZEK != 0
778 struct hw_mem_hole_info mem_hole;
779 u32 reset_memhole = 1;
780#endif
781
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800782 pci_tolm = 0xffffffffUL;
783 for (link = dev->link_list; link; link = link->next) {
784 pci_tolm = find_pci_tolm(link);
785 }
786
787 // FIXME handle interleaved nodes. If you fix this here, please fix
788 // amdk8, too.
789 mmio_basek = pci_tolm >> 10;
790 /* Round mmio_basek to something the processor can support */
791 mmio_basek &= ~((1 << 6) -1);
792
793 // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
794 // MMIO hole. If you fix this here, please fix amdk8, too.
795 /* Round the mmio hole to 64M */
796 mmio_basek &= ~((64*1024) - 1);
797
798#if CONFIG_HW_MEM_HOLE_SIZEK != 0
799 /* if the hw mem hole is already set in raminit stage, here we will compare
800 * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
801 * use hole_basek as mmio_basek and we don't need to reset hole.
802 * otherwise We reset the hole to the mmio_basek
803 */
804
805 mem_hole = get_hw_mem_hole_info();
806
807 // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
808 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
809 mmio_basek = mem_hole.hole_startk;
810 reset_memhole = 0;
811 }
812#endif
813
814 idx = 0x10;
815 for (i = 0; i < node_nums; i++) {
816 dram_base_mask_t d;
817 resource_t basek, limitk, sizek; // 4 1T
818
819 d = get_dram_base_mask(i);
820
821 if (!(d.mask & 1)) continue;
822 basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
Edward O'Callaghanae5fd342014-11-20 19:58:09 +1100823 limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800824
825 sizek = limitk - basek;
826
827 /* see if we need a hole from 0xa0000 to 0xbffff */
828 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
829 ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
830 idx += 0x10;
831 basek = (8*64)+(16*16);
832 sizek = limitk - ((8*64)+(16*16));
833
834 }
835
836 //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
837
Kyösti Mälkki26c65432014-06-26 05:30:54 +0300838 /* split the region to accommodate pci memory space */
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800839 if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) {
840 if (basek <= mmio_basek) {
841 unsigned pre_sizek;
842 pre_sizek = mmio_basek - basek;
843 if (pre_sizek>0) {
844 ram_resource(dev, (idx | i), basek, pre_sizek);
845 idx += 0x10;
846 sizek -= pre_sizek;
Kyösti Mälkki2b790f62013-09-03 05:25:57 +0300847 if (!ramtop)
848 ramtop = mmio_basek * 1024;
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800849 }
850 basek = mmio_basek;
851 }
852 if ((basek + sizek) <= 4*1024*1024) {
853 sizek = 0;
854 }
855 else {
856 uint64_t topmem2 = bsp_topmem2();
857 basek = 4*1024*1024;
858 sizek = topmem2/1024 - basek;
859 }
860 }
861
862 ram_resource(dev, (idx | i), basek, sizek);
863 idx += 0x10;
864 printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
865 i, mmio_basek, basek, limitk);
Kyösti Mälkki2b790f62013-09-03 05:25:57 +0300866 if (!ramtop)
867 ramtop = limitk * 1024;
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800868 }
869
870#if CONFIG_GFXUMA
Kyösti Mälkki2b790f62013-09-03 05:25:57 +0300871 set_top_of_ram(uma_memory_base);
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800872 uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
Kyösti Mälkki2b790f62013-09-03 05:25:57 +0300873#else
874 set_top_of_ram(ramtop);
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800875#endif
876
877 for(link = dev->link_list; link; link = link->next) {
878 if (link->children) {
879 assign_resources(link);
880 }
881 }
882}
883
884static struct device_operations pci_domain_ops = {
885 .read_resources = domain_read_resources,
886 .set_resources = domain_set_resources,
887 .enable_resources = domain_enable_resources,
Edward O'Callaghane9e1d7a2015-01-02 15:11:49 +1100888 .init = DEVICE_NOOP,
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800889 .scan_bus = pci_domain_scan_bus,
890 .ops_pci_bus = pci_bus_default_ops,
891};
892
893static void sysconf_init(device_t dev) // first node
894{
895 sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
896 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
897}
898
899static void add_more_links(device_t dev, unsigned total_links)
900{
901 struct bus *link, *last = NULL;
902 int link_num;
903
904 for (link = dev->link_list; link; link = link->next)
905 last = link;
906
907 if (last) {
908 int links = total_links - last->link_num;
909 link_num = last->link_num;
910 if (links > 0) {
911 link = malloc(links*sizeof(*link));
912 if (!link)
913 die("Couldn't allocate more links!\n");
914 memset(link, 0, links*sizeof(*link));
915 last->next = link;
916 }
917 }
918 else {
919 link_num = -1;
920 link = malloc(total_links*sizeof(*link));
921 memset(link, 0, total_links*sizeof(*link));
922 dev->link_list = link;
923 }
924
925 for (link_num = link_num + 1; link_num < total_links; link_num++) {
926 link->link_num = link_num;
927 link->dev = dev;
928 link->next = link + 1;
929 last = link;
930 link = link->next;
931 }
932 last->next = NULL;
933}
934
Kyösti Mälkki580e7222015-03-19 21:04:23 +0200935static void cpu_bus_scan(device_t dev)
Siyuan Wang3e32cc02013-07-09 17:16:20 +0800936{
937 struct bus *cpu_bus;
938 device_t dev_mc;
939#if CONFIG_CBB
940 device_t pci_domain;
941#endif
942 int i,j;
943 int coreid_bits;
944 int core_max = 0;
945 unsigned ApicIdCoreIdSize;
946 unsigned core_nums;
947 int siblings = 0;
948 unsigned int family;
949
950#if CONFIG_CBB
951 dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
952 if (dev_mc && dev_mc->bus) {
953 printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
954 pci_domain = dev_mc->bus->dev;
955 if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
956 printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
957 dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
958 printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
959 } else {
960 printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
961 }
962 printk(BIOS_DEBUG, "\n");
963 }
964 dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
965 if (!dev_mc) {
966 dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
967 if (dev_mc && dev_mc->bus) {
968 printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
969 pci_domain = dev_mc->bus->dev;
970 if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
971 if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
972 printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
973 dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
974 printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
975 while (dev_mc) {
976 printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
977 dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
978 printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
979 dev_mc = dev_mc->sibling;
980 }
981 }
982 }
983 }
984 }
985#endif
986 dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
987 if (!dev_mc) {
988 printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
989 die("");
990 }
991 sysconf_init(dev_mc);
992#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
993 if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe
994 if (pci_domain->link_list && !pci_domain->link_list->next) {
995 struct bus *new_link = new_link(pci_domain);
996 pci_domain->link_list->next = new_link;
997 new_link->link_num = 1;
998 new_link->dev = pci_domain;
999 new_link->children = 0;
1000 printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain));
1001 }
1002 pci_domain->link_list->next->secondary = CONFIG_CBB - 1;
1003 }
1004#endif
1005
1006 /* Get Max Number of cores(MNC) */
1007 coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
1008 core_max = 1 << (coreid_bits & 0x000F); //mnc
1009
1010 ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
1011 if (ApicIdCoreIdSize) {
1012 core_nums = (1 << ApicIdCoreIdSize) - 1;
1013 } else {
1014 core_nums = 3; //quad core
1015 }
1016
1017 /* Find which cpus are present */
1018 cpu_bus = dev->link_list;
1019 for (i = 0; i < node_nums; i++) {
1020 device_t cdb_dev;
1021 unsigned busn, devn;
1022 struct bus *pbus;
1023
1024 busn = CONFIG_CBB;
1025 devn = CONFIG_CDB + i;
1026 pbus = dev_mc->bus;
1027#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
1028 if (i >= 32) {
1029 busn--;
1030 devn -= 32;
1031 pbus = pci_domain->link_list->next;
1032 }
1033#endif
1034
1035 /* Find the cpu's pci device */
1036 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
1037 if (!cdb_dev) {
1038 /* If I am probing things in a weird order
1039 * ensure all of the cpu's pci devices are found.
1040 */
1041 int fn;
1042 for(fn = 0; fn <= 5; fn++) { //FBDIMM?
1043 cdb_dev = pci_probe_dev(NULL, pbus,
1044 PCI_DEVFN(devn, fn));
1045 }
1046 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
1047 } else {
1048 /* Ok, We need to set the links for that device.
1049 * otherwise the device under it will not be scanned
1050 */
Kyösti Mälkki2a2d6132015-02-04 13:25:37 +02001051 add_more_links(cdb_dev, 4);
Siyuan Wang3e32cc02013-07-09 17:16:20 +08001052 }
1053
1054 family = cpuid_eax(1);
1055 family = (family >> 20) & 0xFF;
1056 if (family == 1) { //f10
1057 u32 dword;
1058 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
1059 dword = pci_read_config32(cdb_dev, 0xe8);
1060 siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
1061 } else if (family == 7) {//f16
1062 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5));
1063 if (cdb_dev && cdb_dev->enabled) {
1064 siblings = pci_read_config32(cdb_dev, 0x84);
1065 siblings &= 0xFF;
1066 }
1067 } else {
1068 siblings = 0; //default one core
1069 }
1070 int enable_node = cdb_dev && cdb_dev->enabled;
1071 printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
1072 dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
1073
1074 for (j = 0; j <= siblings; j++ ) {
1075 extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
1076 u32 modules = TopologyConfiguration.PlatformNumberOfModules;
1077 u32 lapicid_start = 0;
1078
1079 /*
1080 * APIC ID calucation is tightly coupled with AGESA v5 code.
1081 * This calculation MUST match the assignment calculation done
1082 * in LocalApicInitializationAtEarly() function.
1083 * And reference GetLocalApicIdForCore()
1084 *
1085 * Apply apic enumeration rules
1086 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
1087 * put the local-APICs at m..z
1088 *
1089 * This is needed because many IO-APIC devices only have 4 bits
1090 * for their APIC id and therefore must reside at 0..15
1091 */
1092#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */
1093#define CFG_PLAT_NUM_IO_APICS 3
1094#endif
1095 if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) {
1096 lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max;
1097 lapicid_start = (lapicid_start + 1) * core_max;
1098 printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
1099 }
1100 u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
1101 printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
1102 i, j, apic_id);
1103
1104 device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
1105 if (cpu)
1106 amd_cpu_topology(cpu, i, j);
1107 } //j
1108 }
Siyuan Wang3e32cc02013-07-09 17:16:20 +08001109}
1110
1111static void cpu_bus_init(device_t dev)
1112{
1113 initialize_cpus(dev->link_list);
1114}
1115
Siyuan Wang3e32cc02013-07-09 17:16:20 +08001116static struct device_operations cpu_bus_ops = {
Edward O'Callaghan66c65322014-11-21 01:43:38 +11001117 .read_resources = DEVICE_NOOP,
1118 .set_resources = DEVICE_NOOP,
Edward O'Callaghan812d2a42014-10-31 08:17:23 +11001119 .enable_resources = DEVICE_NOOP,
Siyuan Wang3e32cc02013-07-09 17:16:20 +08001120 .init = cpu_bus_init,
1121 .scan_bus = cpu_bus_scan,
1122};
1123
1124static void root_complex_enable_dev(struct device *dev)
1125{
1126 static int done = 0;
1127
1128 /* Do not delay UMA setup, as a device on the PCI bus may evaluate
1129 the global uma_memory variables already in its enable function. */
1130 if (!done) {
1131 setup_bsp_ramtop();
1132 setup_uma_memory();
1133 done = 1;
1134 }
1135
1136 /* Set the operations if it is a special bus type */
1137 if (dev->path.type == DEVICE_PATH_DOMAIN) {
1138 dev->ops = &pci_domain_ops;
1139 } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
1140 dev->ops = &cpu_bus_ops;
1141 }
1142}
1143
1144struct chip_operations northbridge_amd_agesa_family16kb_root_complex_ops = {
1145 CHIP_NAME("AMD FAM16 Root Complex")
1146 .enable_dev = root_complex_enable_dev,
1147};
Bruce Griffith76db07e2013-07-07 02:06:53 -06001148
1149/*********************************************************************
1150 * Change the vendor / device IDs to match the generic VBIOS header. *
1151 *********************************************************************/
1152u32 map_oprom_vendev(u32 vendev)
1153{
1154 u32 new_vendev = vendev;
1155
1156 switch(vendev) {
1157 case 0x10029830:
1158 case 0x10029831:
1159 case 0x10029832:
1160 case 0x10029833:
1161 case 0x10029834:
1162 case 0x10029835:
1163 case 0x10029836:
1164 case 0x10029837:
1165 case 0x10029838:
1166 case 0x10029839:
1167 case 0x1002983A:
1168 case 0x1002983D:
1169 new_vendev = 0x10029830; // This is the default value in AMD-generated VBIOS
1170 break;
1171 default:
1172 break;
1173 }
1174
1175 if (vendev != new_vendev)
1176 printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev);
1177
1178 return new_vendev;
1179}