Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 21 | #include <stdint.h> |
| 22 | #include <device/pci_def.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <device/pnp_def.h> |
Carl-Daniel Hailfinger | 2ee6779 | 2008-10-01 12:52:52 +0000 | [diff] [blame] | 25 | #include <stdlib.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 26 | #include <console/console.h> |
Uwe Hermann | 115c5b9 | 2010-10-09 17:00:18 +0000 | [diff] [blame] | 27 | #include "southbridge/intel/i82371eb/i82371eb.h" |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 28 | #include "northbridge/intel/i440bx/raminit.h" |
Stefan Reinauer | ae5e11d | 2012-04-27 02:31:28 +0200 | [diff] [blame] | 29 | #include "drivers/pc80/udelay_io.c" |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 30 | #include "lib/delay.c" |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 31 | #include "cpu/x86/bist.h" |
Edward O'Callaghan | 6fb379a | 2014-06-01 17:38:22 +1000 | [diff] [blame] | 32 | #include <superio/winbond/common/winbond.h> |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 33 | /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ |
Edward O'Callaghan | 6fb379a | 2014-06-01 17:38:22 +1000 | [diff] [blame] | 34 | #include <superio/winbond/w83977tf/w83977tf.h> |
Uwe Hermann | 6f2d20e | 2010-10-06 19:32:39 +0000 | [diff] [blame] | 35 | #include <lib.h> |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 36 | |
| 37 | /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ |
| 38 | #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) |
| 39 | |
Uwe Hermann | 115c5b9 | 2010-10-09 17:00:18 +0000 | [diff] [blame] | 40 | int spd_read_byte(unsigned int device, unsigned int address) |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 41 | { |
| 42 | return smbus_read_byte(device, address); |
| 43 | } |
| 44 | |
Uwe Hermann | 0865b4d | 2010-09-19 21:12:05 +0000 | [diff] [blame] | 45 | /* |
| 46 | * ASUS P3B-F specific SPD enable magic. |
| 47 | * |
| 48 | * Setting the byte at offset 0x37 in the PM I/O space to 0x6f will make the |
| 49 | * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD |
| 50 | * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which |
| 51 | * will make RAM init fail. |
| 52 | * |
| 53 | * Tested values for PM I/O offset 0x37: |
| 54 | * 0x67: 11 00 111: Only SMBus/I2C offsets 0x48/0x49/0x2d accessible |
| 55 | * 0x6f: 11 01 111: Only SMBus/I2C offsets 0x50-0x53 (SPD) accessible |
| 56 | * 0x77: 11 10 111: Only SMBus/I2C offset 0x69 accessible |
| 57 | * |
| 58 | * PM I/O space offset 0x37 is GPOREG[31:24], i.e. it controls the GPIOs |
| 59 | * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28 |
| 60 | * control which SMBus/I2C offsets can be accessed. |
| 61 | */ |
| 62 | static void enable_spd(void) |
| 63 | { |
| 64 | outb(0x6f, PM_IO_BASE + 0x37); |
| 65 | } |
| 66 | |
| 67 | /* |
| 68 | * Disable SPD access after RAM init to allow access to SMBus/I2C offsets |
| 69 | * 0x48/0x49/0x2d, which is required e.g. by lm-sensors. |
| 70 | */ |
| 71 | static void disable_spd(void) |
| 72 | { |
| 73 | outb(0x67, PM_IO_BASE + 0x37); |
| 74 | } |
| 75 | |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 76 | #include <cpu/intel/romstage.h> |
Uwe Hermann | 6f2d20e | 2010-10-06 19:32:39 +0000 | [diff] [blame] | 77 | void main(unsigned long bist) |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 78 | { |
Edward O'Callaghan | 6fb379a | 2014-06-01 17:38:22 +1000 | [diff] [blame] | 79 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 80 | console_init(); |
| 81 | report_bist_failure(bist); |
Uwe Hermann | 9095092 | 2009-10-04 23:50:06 +0000 | [diff] [blame] | 82 | |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 83 | enable_smbus(); |
Uwe Hermann | 0865b4d | 2010-09-19 21:12:05 +0000 | [diff] [blame] | 84 | enable_pm(); |
| 85 | |
| 86 | enable_spd(); |
| 87 | |
Uwe Hermann | 6f2d20e | 2010-10-06 19:32:39 +0000 | [diff] [blame] | 88 | dump_spd_registers(); |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 89 | sdram_set_registers(); |
| 90 | sdram_set_spd_registers(); |
| 91 | sdram_enable(); |
Uwe Hermann | 0865b4d | 2010-09-19 21:12:05 +0000 | [diff] [blame] | 92 | |
| 93 | disable_spd(); |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 94 | } |