blob: a1674d3c13262bab9f054fdd656e11aa72f494a3 [file] [log] [blame]
Rex-BC Chen74a06292021-09-09 18:43:22 +08001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <bootmode.h>
4#include <boot/coreboot_tables.h>
Grzegorz Bernacki7758b472023-06-14 12:01:32 +00005#include <drivers/tpm/cr50.h>
Yu-Ping Wuc7730dd2022-06-28 17:29:20 +08006#include <ec/google/chromeec/ec.h>
Rex-BC Chen580150d2021-11-17 15:50:38 +08007#include <gpio.h>
Yu-Ping Wuc7730dd2022-06-28 17:29:20 +08008#include <stdbool.h>
Rex-BC Chen580150d2021-11-17 15:50:38 +08009
10#include "gpio.h"
11
12void setup_chromeos_gpios(void)
13{
Rex-BC Chenee569982021-12-09 11:35:02 +080014 /* Set up open-drain pins */
15 gpio_input(GPIO_SAR_INT_ODL);
16 gpio_input(GPIO_BT_WAKE_AP_ODL);
17 gpio_input(GPIO_WIFI_INT_ODL);
18 gpio_input(GPIO_DPBRDG_INT_ODL);
19 gpio_input(GPIO_EDPBRDG_INT_ODL);
20 gpio_input(GPIO_EC_AP_HPD_OD);
21 gpio_input(GPIO_TCHPAD_INT_ODL);
22 gpio_input(GPIO_TCHSCR_INT_1V8_ODL);
23 gpio_input(GPIO_EC_AP_INT_ODL);
24 gpio_input(GPIO_EC_IN_RW_ODL);
25 gpio_input(GPIO_GSC_AP_INT_ODL);
26 gpio_input(GPIO_AP_WP_ODL);
27 gpio_input(GPIO_HP_INT_ODL);
28 gpio_input(GPIO_PEN_EJECT_OD);
29 gpio_input(GPIO_UCAM_DET_ODL);
30
31 /* Set up GPIOs */
Rex-BC Chen580150d2021-11-17 15:50:38 +080032 gpio_output(GPIO_RESET, 0);
Rex-BC Chenee569982021-12-09 11:35:02 +080033 gpio_output(GPIO_XHCI_DONE, 0);
34 gpio_output(GPIO_EN_SPK, 0);
Rex-BC Chen580150d2021-11-17 15:50:38 +080035}
Rex-BC Chen74a06292021-09-09 18:43:22 +080036
37void fill_lb_gpios(struct lb_gpios *gpios)
38{
Rex-BC Chen580150d2021-11-17 15:50:38 +080039 struct lb_gpio chromeos_gpios[] = {
Rex-BC Chenee569982021-12-09 11:35:02 +080040 {GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"},
41 {GPIO_EC_IN_RW_ODL.id, ACTIVE_LOW, -1, "EC in RW"},
42 {GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"},
Rex-BC Chen580150d2021-11-17 15:50:38 +080043 {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"},
44 };
45 lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
Rex-BC Chen74a06292021-09-09 18:43:22 +080046}
Rex-BC Chene96861f2021-11-18 15:02:35 +080047
48int get_ec_is_trusted(void)
49{
Yu-Ping Wuc7730dd2022-06-28 17:29:20 +080050 uint32_t rev;
51 bool has_cr50 = false;
52
53 /*
54 * Kingler and Krabby's rev 0 boards both use Cr50 instead of Ti50. In order to share
55 * the same firmware with newer rev, get the board rev from CBI, and ignore
56 * TPM_GOOGLE_TI50 when rev is 0.
57 */
58 if (CONFIG(BOARD_GOOGLE_KINGLER) || CONFIG(BOARD_GOOGLE_KRABBY)) {
59 if (google_chromeec_cbi_get_board_version(&rev) == 0 && rev == 0)
60 has_cr50 = true;
61 }
62
Yu-Ping Wu7f339c62022-06-07 16:10:04 +080063 /* With Ti50, VB2_CONTEXT_EC_TRUSTED should be set according to the boot mode. */
Yu-Ping Wuc7730dd2022-06-28 17:29:20 +080064 if (CONFIG(TPM_GOOGLE_TI50) && !has_cr50)
Yu-Ping Wu7f339c62022-06-07 16:10:04 +080065 return 0;
66
Rex-BC Chene96861f2021-11-18 15:02:35 +080067 /* EC is trusted if not in RW. This is active low. */
Rex-BC Chenee569982021-12-09 11:35:02 +080068 return !!gpio_get(GPIO_EC_IN_RW_ODL);
Rex-BC Chene96861f2021-11-18 15:02:35 +080069}
Rex-BC Chen858481e2021-11-18 15:43:40 +080070
Grzegorz Bernacki7758b472023-06-14 12:01:32 +000071int cr50_plat_irq_status(void)
Rex-BC Chen858481e2021-11-18 15:43:40 +080072{
Rex-BC Chenee569982021-12-09 11:35:02 +080073 return gpio_eint_poll(GPIO_GSC_AP_INT_ODL);
Rex-BC Chen858481e2021-11-18 15:43:40 +080074}