Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 DMP Electronics Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <delay.h> |
| 17 | #include <stdlib.h> |
| 18 | #include <string.h> |
| 19 | #include <arch/io.h> |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <device/pci_ops.h> |
| 26 | |
| 27 | /* Vortex86EX IDE to SD/STAT controller need to enable ATA decoder and |
| 28 | * setup timing. */ |
| 29 | |
| 30 | /* |
| 31 | * Primary ATA Timing Register (PATR) - Offset 40-41h |
| 32 | * Secondary ATA Timing Register (PATR) - Offset 42-43h |
| 33 | * |
| 34 | * Bit R/W Default Description |
| 35 | * 15 R/W 0h ATA Decode Enable. Decode the I/O addressing ranges assigned to this controller. |
| 36 | * 1: Enabled. |
| 37 | * 0: Disabled. |
| 38 | * 14 R/W 0b Device 1 ATA Timing Register Enable |
| 39 | * 1: Enable the device 1 ATA timing. |
| 40 | * 0: Disable the device 1 ATA timing |
| 41 | * 13-12 R/W 0h IORDY Sample Mode. Sets the setup time before IORDY are sampled. |
| 42 | * 00: PIO-0 |
| 43 | * 10: PIO-2, SW-2 |
| 44 | * 10: PIO-3, PIO-4, MW-1, MW-2 |
| 45 | * 11: Reserved |
| 46 | * 11-10 RO 0h Reserved |
| 47 | * 9-8 R/W 0h Recovery Mode. Sets the hold time after IORDY are sampled. |
| 48 | * 00: PIO-0, PIO-2, SW-2 |
| 49 | * 10: PIO-3, MW-1 |
| 50 | * 10: Reserved |
| 51 | * 11: PIO-4, MW-2 |
| 52 | * 7 R/W 0b DMA Timing Enable Only Select 1 |
| 53 | * 1: Enable the device timings for DMA operation for device 1 |
| 54 | * 0: Disable the device timings for DMA operation for device 1 |
| 55 | * 6 R/W 0b ATA/ATAPI Device Indicator 1 |
| 56 | * 1: Indicate presence od an ATA device |
| 57 | * 0: Indicate presence od an ATAPI device |
| 58 | * 5 R/W 0b IORDY Sample Point Enabled Select 1 |
| 59 | * 1: Enable IORDY sample for PIO transfers for device 1 |
| 60 | * 0: Disable IORDY sample for PIO transfers for device 1 |
| 61 | * 4 R/W 0b Fast Drive Timing Select 1 |
| 62 | * 1: Enable faster than PIO-0 timing modes for device 1 |
| 63 | * 0: Disable faster than PIO-0 timing modes for device 1 |
| 64 | * 3 R/W 0b DMA Timing Enable Only Select 0 |
| 65 | * 1: Enable the device timings for DMA operation for device 0 |
| 66 | * 0: Disable the device timings for DMA operation for device 0 |
| 67 | * 2 R/W 0b ATA/ATAPI Device Indicator 0 |
| 68 | * 1: Indicate presence od an ATA device |
| 69 | * 0: Indicate presence od an ATAPI device |
| 70 | * 1 R/W 0b IORDY Sample Point Enabled Select 0 |
| 71 | * 1: Enable IORDY sample for PIO transfers for device 0 |
| 72 | * 0: Disable IORDY sample for PIO transfers for device 0 |
| 73 | * 0 R/W 0b Fast Drive Timing Select 0 |
| 74 | * 1: Enable faster than PIO-0 timing modes for device 0 |
| 75 | * 0: Disable faster than PIO-0 timing modes for device 0 |
| 76 | * */ |
| 77 | |
| 78 | static void init_ide_ata_timing(struct device *dev) |
| 79 | { |
| 80 | u16 ata_timing_pri, ata_timing_sec; |
| 81 | u32 ata_timing_reg32; |
| 82 | /* Primary channel is SD. */ |
| 83 | #if CONFIG_IDE1_ENABLE |
| 84 | ata_timing_pri = 0x8000; |
| 85 | #else |
| 86 | ata_timing_pri = 0x0000; // Disable this channel. |
| 87 | #endif |
| 88 | /* Secondary channel is SATA. */ |
| 89 | #if CONFIG_IDE2_ENABLE |
| 90 | ata_timing_sec = 0xa30f; // This setting value works well. |
| 91 | #else |
| 92 | ata_timing_sec = 0x0000; // Disable this channel. |
| 93 | #endif |
| 94 | ata_timing_reg32 = (ata_timing_sec << 16) | ata_timing_pri; |
| 95 | pci_write_config32(dev, 0x40, ata_timing_reg32); |
| 96 | #if CONFIG_IDE_NATIVE_MODE |
| 97 | /* Set both IDE channels to native mode. */ |
| 98 | u8 prog_if; |
| 99 | prog_if = pci_read_config8(dev, 0x09); |
| 100 | prog_if |= 5; |
| 101 | pci_write_config8(dev, 0x09, prog_if); |
| 102 | #endif |
| 103 | /* MMC function enable. */ |
| 104 | u32 sd_ctrl_reg; |
| 105 | sd_ctrl_reg = pci_read_config32(dev, 0x94); |
| 106 | sd_ctrl_reg |= 0x0200; |
| 107 | pci_write_config32(dev, 0x94, sd_ctrl_reg); |
| 108 | printk(BIOS_INFO, "Vortex86EX IDE controller ATA TIMING reg = %08x\n", ata_timing_reg32); |
| 109 | } |
| 110 | |
| 111 | static void setup_std_ide_compatible(struct device *dev) |
| 112 | { |
| 113 | #if CONFIG_IDE_STANDARD_COMPATIBLE |
| 114 | // Misc Control Register (MCR) Offset 90h |
| 115 | // bit 0 = Vendor ID Access, bit 1 = Device ID Access. |
| 116 | u8 mcr; |
| 117 | u16 vendor = (u16) (CONFIG_IDE_COMPATIBLE_SELECTION >> 16); |
| 118 | u16 device = (u16) (CONFIG_IDE_COMPATIBLE_SELECTION & 0xffff); |
| 119 | // unlock vendor/device ID access bits. |
| 120 | mcr = pci_read_config8(dev, 0x90); |
| 121 | pci_write_config8(dev, 0x90, mcr | 3); |
| 122 | pci_write_config16(dev, 0x00, vendor); |
| 123 | pci_write_config16(dev, 0x02, device); |
| 124 | // restore lock bits. |
| 125 | pci_write_config8(dev, 0x90, mcr); |
| 126 | #endif |
| 127 | } |
| 128 | |
| 129 | static void vortex_ide_init(struct device *dev) |
| 130 | { |
| 131 | if (dev->device == 0x1010) { |
| 132 | // This is SX/old DX IDE controller. |
| 133 | // Set IOCFG bit 15/13 : IDE Decoder Enable for Primary/Secondary channel. |
| 134 | u16 iocfg = 0xa000; |
| 135 | pci_write_config16(dev, 0x40, iocfg); |
| 136 | } else if (dev->device == 0x1011 || dev->device == 0x1012) { |
| 137 | // This is new DX/MX/MX+/DX2 IDE controller. |
| 138 | init_ide_ata_timing(dev); |
| 139 | setup_std_ide_compatible(dev); |
| 140 | } |
| 141 | } |
| 142 | |
| 143 | static struct device_operations vortex_ide_ops = { |
| 144 | .read_resources = pci_dev_read_resources, |
| 145 | .set_resources = pci_dev_set_resources, |
| 146 | .enable_resources = pci_dev_enable_resources, |
| 147 | .init = vortex_ide_init, |
| 148 | .scan_bus = 0, |
| 149 | }; |
| 150 | |
| 151 | static const struct pci_driver vortex_ide_driver_1010 __pci_driver = { |
| 152 | .ops = &vortex_ide_ops, |
| 153 | .vendor = PCI_VENDOR_ID_RDC, |
| 154 | .device = 0x1010, |
| 155 | }; |
| 156 | |
| 157 | static const struct pci_driver vortex_ide_driver_1011 __pci_driver = { |
| 158 | .ops = &vortex_ide_ops, |
| 159 | .vendor = PCI_VENDOR_ID_RDC, |
| 160 | .device = 0x1011, |
| 161 | }; |
| 162 | |
| 163 | static const struct pci_driver vortex_ide_driver_1012 __pci_driver = { |
| 164 | .ops = &vortex_ide_ops, |
| 165 | .vendor = PCI_VENDOR_ID_RDC, |
| 166 | .device = 0x1012, |
| 167 | }; |