Timothy Pearson | c3fcdcc | 2015-09-05 17:46:38 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
| 5 | * Copyright (C) 2009 Advanced Micro Devices, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Timothy Pearson | c3fcdcc | 2015-09-05 17:46:38 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | Scope(\) { |
Timothy Pearson | 56c8ef9 | 2015-08-14 02:50:44 -0500 | [diff] [blame] | 18 | Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ |
| 19 | Name(HPBA, 0xFED00000) /* Base address of HPET table */ |
Timothy Pearson | c3fcdcc | 2015-09-05 17:46:38 -0500 | [diff] [blame] | 20 | |
| 21 | /* PIC IRQ mapping registers, C00h-C01h */ |
| 22 | OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) |
| 23 | Field(PRQM, ByteAcc, NoLock, Preserve) { |
| 24 | PRQI, 0x00000008, |
| 25 | PRQD, 0x00000008, /* Offset: 1h */ |
| 26 | } |
| 27 | IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { |
| 28 | PINA, 0x00000008, /* Index 0 */ |
| 29 | PINB, 0x00000008, /* Index 1 */ |
| 30 | PINC, 0x00000008, /* Index 2 */ |
| 31 | PIND, 0x00000008, /* Index 3 */ |
| 32 | AINT, 0x00000008, /* Index 4 */ |
| 33 | SINT, 0x00000008, /* Index 5 */ |
| 34 | , 0x00000008, /* Index 6 */ |
| 35 | AAUD, 0x00000008, /* Index 7 */ |
| 36 | AMOD, 0x00000008, /* Index 8 */ |
| 37 | PINE, 0x00000008, /* Index 9 */ |
| 38 | PINF, 0x00000008, /* Index A */ |
| 39 | PING, 0x00000008, /* Index B */ |
| 40 | PINH, 0x00000008, /* Index C */ |
| 41 | } |
| 42 | |
| 43 | /* PCI Error control register */ |
| 44 | OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) |
| 45 | Field(PERC, ByteAcc, NoLock, Preserve) { |
| 46 | SENS, 0x00000001, |
| 47 | PENS, 0x00000001, |
| 48 | SENE, 0x00000001, |
| 49 | PENE, 0x00000001, |
| 50 | } |
| 51 | |
| 52 | Scope(\_SB) { |
| 53 | /* PCIe Configuration Space for 16 busses */ |
| 54 | OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ |
| 55 | Field(PCFG, ByteAcc, NoLock, Preserve) { |
| 56 | /* Byte offsets are computed using the following technique: |
| 57 | * ((bus number + 1) * ((device number * 8) * 4096)) + register offset |
| 58 | * The 8 comes from 8 functions per device, and 4096 bytes per function config space |
| 59 | */ |
| 60 | Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ |
| 61 | STB5, 32, |
| 62 | Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ |
| 63 | PT0D, 1, |
| 64 | PT1D, 1, |
| 65 | PT2D, 1, |
| 66 | PT3D, 1, |
| 67 | PT4D, 1, |
| 68 | PT5D, 1, |
| 69 | PT6D, 1, |
| 70 | PT7D, 1, |
| 71 | PT8D, 1, |
| 72 | PT9D, 1, |
| 73 | Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ |
| 74 | SBIE, 1, |
| 75 | SBME, 1, |
| 76 | Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ |
| 77 | SBRI, 8, |
| 78 | Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ |
| 79 | SBB1, 32, |
| 80 | Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ |
| 81 | ,14, |
| 82 | P92E, 1, /* Port92 decode enable */ |
| 83 | } |
| 84 | |
| 85 | OperationRegion(SB5, SystemMemory, STB5, 0x1000) |
| 86 | Field(SB5, AnyAcc, NoLock, Preserve){ |
| 87 | /* Port 0 */ |
| 88 | Offset(0x120), /* Port 0 Task file status */ |
| 89 | P0ER, 1, |
| 90 | , 2, |
| 91 | P0DQ, 1, |
| 92 | , 3, |
| 93 | P0BY, 1, |
| 94 | Offset(0x128), /* Port 0 Serial ATA status */ |
| 95 | P0DD, 4, |
| 96 | , 4, |
| 97 | P0IS, 4, |
| 98 | Offset(0x12C), /* Port 0 Serial ATA control */ |
| 99 | P0DI, 4, |
| 100 | Offset(0x130), /* Port 0 Serial ATA error */ |
| 101 | , 16, |
| 102 | P0PR, 1, |
| 103 | |
| 104 | /* Port 1 */ |
| 105 | offset(0x1A0), /* Port 1 Task file status */ |
| 106 | P1ER, 1, |
| 107 | , 2, |
| 108 | P1DQ, 1, |
| 109 | , 3, |
| 110 | P1BY, 1, |
| 111 | Offset(0x1A8), /* Port 1 Serial ATA status */ |
| 112 | P1DD, 4, |
| 113 | , 4, |
| 114 | P1IS, 4, |
| 115 | Offset(0x1AC), /* Port 1 Serial ATA control */ |
| 116 | P1DI, 4, |
| 117 | Offset(0x1B0), /* Port 1 Serial ATA error */ |
| 118 | , 16, |
| 119 | P1PR, 1, |
| 120 | |
| 121 | /* Port 2 */ |
| 122 | Offset(0x220), /* Port 2 Task file status */ |
| 123 | P2ER, 1, |
| 124 | , 2, |
| 125 | P2DQ, 1, |
| 126 | , 3, |
| 127 | P2BY, 1, |
| 128 | Offset(0x228), /* Port 2 Serial ATA status */ |
| 129 | P2DD, 4, |
| 130 | , 4, |
| 131 | P2IS, 4, |
| 132 | Offset(0x22C), /* Port 2 Serial ATA control */ |
| 133 | P2DI, 4, |
| 134 | Offset(0x230), /* Port 2 Serial ATA error */ |
| 135 | , 16, |
| 136 | P2PR, 1, |
| 137 | |
| 138 | /* Port 3 */ |
| 139 | Offset(0x2A0), /* Port 3 Task file status */ |
| 140 | P3ER, 1, |
| 141 | , 2, |
| 142 | P3DQ, 1, |
| 143 | , 3, |
| 144 | P3BY, 1, |
| 145 | Offset(0x2A8), /* Port 3 Serial ATA status */ |
| 146 | P3DD, 4, |
| 147 | , 4, |
| 148 | P3IS, 4, |
| 149 | Offset(0x2AC), /* Port 3 Serial ATA control */ |
| 150 | P3DI, 4, |
| 151 | Offset(0x2B0), /* Port 3 Serial ATA error */ |
| 152 | , 16, |
| 153 | P3PR, 1, |
| 154 | } |
| 155 | |
| 156 | Method(CIRQ, 0x00, NotSerialized){ |
| 157 | Store(0, PINA) |
| 158 | Store(0, PINB) |
| 159 | Store(0, PINC) |
| 160 | Store(0, PIND) |
| 161 | Store(0, PINE) |
| 162 | Store(0, PINF) |
| 163 | Store(0, PING) |
| 164 | Store(0, PINH) |
| 165 | } |
| 166 | |
| 167 | /* set "A", 8259 interrupts */ |
| 168 | Name (PRSA, ResourceTemplate () { |
| 169 | IRQ(Level, ActiveLow, Exclusive) {4, 7, 10, 11, 12, 14, 15} |
| 170 | }) |
| 171 | |
| 172 | Method (CRSA, 1, Serialized) { |
| 173 | Name (LRTL, ResourceTemplate() { |
| 174 | IRQ(Level, ActiveLow, Shared) {15} |
| 175 | }) |
| 176 | CreateWordField(LRTL, 1, LIRQ) |
| 177 | ShiftLeft(1, Arg0, LIRQ) |
| 178 | Return (LRTL) |
| 179 | } |
| 180 | |
| 181 | Method (SRSA, 1, Serialized) { |
| 182 | CreateWordField(Arg0, 1, LIRQ) |
| 183 | FindSetRightBit(LIRQ, Local0) |
| 184 | if (Local0) { |
| 185 | Decrement(Local0) |
| 186 | } |
| 187 | Return (Local0) |
| 188 | } |
| 189 | |
| 190 | Device(LNKA) { |
| 191 | Name(_HID, EISAID("PNP0C0F")) |
| 192 | Name(_UID, 1) |
| 193 | Method(_STA, 0) { |
| 194 | if (PINA) { |
| 195 | Return(0x0B) /* LNKA is invisible */ |
| 196 | } else { |
| 197 | Return(0x09) /* LNKA is disabled */ |
| 198 | } |
| 199 | } |
| 200 | Method(_DIS, 0) { |
| 201 | Store(0, PINA) |
| 202 | } |
| 203 | Method(_PRS, 0) { |
| 204 | Return (PRSA) |
| 205 | } |
| 206 | Method (_CRS, 0, Serialized) { |
| 207 | Return (CRSA(PINA)) |
| 208 | } |
| 209 | Method (_SRS, 1, Serialized) { |
| 210 | Store (SRSA(Arg0), PINA) |
| 211 | } |
| 212 | } |
| 213 | |
| 214 | Device(LNKB) { |
| 215 | Name(_HID, EISAID("PNP0C0F")) |
| 216 | Name(_UID, 2) |
| 217 | Method(_STA, 0) { |
| 218 | if (PINB) { |
| 219 | Return(0x0B) /* LNKB is invisible */ |
| 220 | } else { |
| 221 | Return(0x09) /* LNKB is disabled */ |
| 222 | } |
| 223 | } |
| 224 | Method(_DIS, 0) { |
| 225 | Store(0, PINB) |
| 226 | } |
| 227 | Method(_PRS, 0) { |
| 228 | Return (PRSA) |
| 229 | } |
| 230 | Method (_CRS, 0, Serialized) { |
| 231 | Return (CRSA(PINB)) |
| 232 | } |
| 233 | Method (_SRS, 1, Serialized) { |
| 234 | Store (SRSA(Arg0), PINB) |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | Device(LNKC) { |
| 239 | Name(_HID, EISAID("PNP0C0F")) |
| 240 | Name(_UID, 3) |
| 241 | Method(_STA, 0) { |
| 242 | if (PINC) { |
| 243 | Return(0x0B) /* LNKC is invisible */ |
| 244 | } else { |
| 245 | Return(0x09) /* LNKC is disabled */ |
| 246 | } |
| 247 | } |
| 248 | Method(_DIS, 0) { |
| 249 | Store(0, PINC) |
| 250 | } |
| 251 | Method(_PRS, 0) { |
| 252 | Return (PRSA) |
| 253 | } |
| 254 | Method (_CRS, 0, Serialized) { |
| 255 | Return (CRSA(PINC)) |
| 256 | } |
| 257 | Method (_SRS, 1, Serialized) { |
| 258 | Store (SRSA(Arg0), PINC) |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | Device(LNKD) { |
| 263 | Name(_HID, EISAID("PNP0C0F")) |
| 264 | Name(_UID, 4) |
| 265 | Method(_STA, 0) { |
| 266 | if (PIND) { |
| 267 | Return(0x0B) /* LNKD is invisible */ |
| 268 | } else { |
| 269 | Return(0x09) /* LNKD is disabled */ |
| 270 | } |
| 271 | } |
| 272 | Method(_DIS, 0) { |
| 273 | Store(0, PIND) |
| 274 | } |
| 275 | Method(_PRS, 0) { |
| 276 | Return (PRSA) |
| 277 | } |
| 278 | Method (_CRS, 0, Serialized) { |
| 279 | Return (CRSA(PIND)) |
| 280 | } |
| 281 | Method (_SRS, 1, Serialized) { |
| 282 | Store (SRSA(Arg0), PIND) |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | Device(LNKE) { |
| 287 | Name(_HID, EISAID("PNP0C0F")) |
| 288 | Name(_UID, 5) |
| 289 | Method(_STA, 0) { |
| 290 | if (PINE) { |
| 291 | Return(0x0B) /* LNKE is invisible */ |
| 292 | } else { |
| 293 | Return(0x09) /* LNKE is disabled */ |
| 294 | } |
| 295 | } |
| 296 | Method(_DIS, 0) { |
| 297 | Store(0, PINE) |
| 298 | } |
| 299 | Method(_PRS, 0) { |
| 300 | Return (PRSA) |
| 301 | } |
| 302 | Method (_CRS, 0, Serialized) { |
| 303 | Return (CRSA(PINE)) |
| 304 | } |
| 305 | Method (_SRS, 1, Serialized) { |
| 306 | Store (SRSA(Arg0), PINE) |
| 307 | } |
| 308 | } |
| 309 | |
| 310 | Device(LNKF) { |
| 311 | Name(_HID, EISAID("PNP0C0F")) |
| 312 | Name(_UID, 6) |
| 313 | Method(_STA, 0) { |
| 314 | if (PINF) { |
| 315 | Return(0x0B) /* LNKF is invisible */ |
| 316 | } else { |
| 317 | Return(0x09) /* LNKF is disabled */ |
| 318 | } |
| 319 | } |
| 320 | Method(_DIS, 0) { |
| 321 | Store(0, PINF) |
| 322 | } |
| 323 | Method(_PRS, 0) { |
| 324 | Return (PRSA) |
| 325 | } |
| 326 | Method (_CRS, 0, Serialized) { |
| 327 | Return (CRSA(PINF)) |
| 328 | } |
| 329 | Method (_SRS, 1, Serialized) { |
| 330 | Store (SRSA(Arg0), PINF) |
| 331 | } |
| 332 | } |
| 333 | |
| 334 | Device(LNKG) { |
| 335 | Name(_HID, EISAID("PNP0C0F")) |
| 336 | Name(_UID, 7) |
| 337 | Method(_STA, 0) { |
| 338 | if (PING) { |
| 339 | Return(0x0B) /* LNKG is invisible */ |
| 340 | } else { |
| 341 | Return(0x09) /* LNKG is disabled */ |
| 342 | } |
| 343 | } |
| 344 | Method(_DIS, 0) { |
| 345 | Store(0, PING) |
| 346 | } |
| 347 | Method(_PRS, 0) { |
| 348 | Return (PRSA) |
| 349 | } |
| 350 | Method (_CRS, 0, Serialized) { |
| 351 | Return (CRSA(PING)) |
| 352 | } |
| 353 | Method (_SRS, 1, Serialized) { |
| 354 | Store (SRSA(Arg0), PING) |
| 355 | } |
| 356 | } |
| 357 | |
| 358 | Device(LNKH) { |
| 359 | Name(_HID, EISAID("PNP0C0F")) |
| 360 | Name(_UID, 8) |
| 361 | Method(_STA, 0) { |
| 362 | if (PINH) { |
| 363 | Return(0x0B) /* LNKH is invisible */ |
| 364 | } else { |
| 365 | Return(0x09) /* LNKH is disabled */ |
| 366 | } |
| 367 | } |
| 368 | Method(_DIS, 0) { |
| 369 | Store(0, PINH) |
| 370 | } |
| 371 | Method(_PRS, 0) { |
| 372 | Return (PRSA) |
| 373 | } |
| 374 | Method (_CRS, 0, Serialized) { |
| 375 | Return (CRSA(PINH)) |
| 376 | } |
| 377 | Method (_SRS, 1, Serialized) { |
| 378 | Store (SRSA(Arg0), PINH) |
| 379 | } |
| 380 | } |
| 381 | |
| 382 | } /* End Scope(_SB) */ |
| 383 | |
| 384 | } /* End Scope(/) */ |