blob: 0b688501219cf0271ff5d3d2da76fa7b738c9727 [file] [log] [blame]
Zheng Baod0985752011-01-20 04:45:48 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Zheng Baod0985752011-01-20 04:45:48 +000014 */
15
16#include <console/console.h>
17#include <device/device.h>
18#include <device/pci.h>
19#include <device/pci_ids.h>
20#include <device/pci_ops.h>
21#include <arch/io.h>
22#include <delay.h>
23#include "sb800.h"
24
25#define HDA_ICII_REG 0x68
Andrew Wuae8d0692013-08-02 19:29:17 +080026#define HDA_ICII_BUSY (1 << 0)
27#define HDA_ICII_VALID (1 << 1)
Zheng Baod0985752011-01-20 04:45:48 +000028
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080029static int set_bits(void *port, u32 mask, u32 val)
Zheng Baod0985752011-01-20 04:45:48 +000030{
31 u32 dword;
32 int count;
33
34 /* Write (val & ~mask) to port */
35 val &= mask;
36 dword = read32(port);
37 dword &= ~mask;
38 dword |= val;
39 write32(port, dword);
40
41 /* Wait for readback of register to
42 * match what was just written to it
43 */
44 count = 50;
45 do {
46 /* Wait 1ms based on BKDG wait time */
47 mdelay(1);
48 dword = read32(port);
49 dword &= mask;
50 } while ((dword != val) && --count);
51
Martin Rothdcf253c2014-12-16 20:51:31 -070052 /* Timeout occurred */
Zheng Baod0985752011-01-20 04:45:48 +000053 if (!count)
54 return -1;
55 return 0;
56}
57
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080058static u32 codec_detect(void *base)
Zheng Baod0985752011-01-20 04:45:48 +000059{
60 u32 dword;
61
62 /* Before Codec detection, we need to set the GPIO167-170 as
63 * AZ_SDINx. */
64 /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
65 if (set_bits(base + 0x08, 1, 0) == -1)
66 goto no_codec;
67
68 /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
69 if (set_bits(base + 0x08, 1, 1) == -1)
70 goto no_codec;
71
72 /* Delay for 1 ms since the BKDG does */
73 mdelay(1);
74
75 /* Read in Codec location (BAR + 0xe)[3..0]*/
76 dword = read32(base + 0xe);
77 dword &= 0x0F;
78 if (!dword)
79 goto no_codec;
80
81 return dword;
82
83no_codec:
84 /* Codec Not found */
85 /* Put HDA back in reset (BAR + 0x8) [0] */
86 set_bits(base + 0x08, 1, 0);
87 printk(BIOS_DEBUG, "No codec!\n");
88 return 0;
89}
90
91/**
92 * Wait 50usec for for the codec to indicate it is ready
93 * no response would imply that the codec is non-operative
94 */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080095static int wait_for_ready(void *base)
Zheng Baod0985752011-01-20 04:45:48 +000096{
97 /* Use a 50 usec timeout - the Linux kernel uses the
98 * same duration */
99
100 int timeout = 50;
101
102 while(timeout--) {
103 u32 dword=read32(base + HDA_ICII_REG);
104 if (!(dword & HDA_ICII_BUSY))
105 return 0;
106 udelay(1);
107 }
108
109 return -1;
110}
111
112/**
113 * Wait 50usec for for the codec to indicate that it accepted
114 * the previous command. No response would imply that the code
115 * is non-operative
116 */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800117static int wait_for_valid(void *base)
Zheng Baod0985752011-01-20 04:45:48 +0000118{
119 /* Use a 50 usec timeout - the Linux kernel uses the
120 * same duration */
121
122 int timeout = 50;
123 while(timeout--) {
124 u32 dword = read32(base + HDA_ICII_REG);
125 if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
126 HDA_ICII_VALID)
127 return 0;
128 udelay(1);
129 }
130
Andrew Wu9361daf2013-08-02 14:45:03 +0800131 return -1;
Zheng Baod0985752011-01-20 04:45:48 +0000132}
133
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800134static void codec_init(void *base, int addr)
Zheng Baod0985752011-01-20 04:45:48 +0000135{
136 u32 dword;
137
138 /* 1 */
139 if (wait_for_ready(base) == -1)
140 return;
141
142 dword = (addr << 28) | 0x000f0000;
143 write32(base + 0x60, dword);
144
145 if (wait_for_valid(base) == -1)
146 return;
147
148 dword = read32(base + 0x64);
149
150 /* 2 */
151 printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
152}
153
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800154static void codecs_init(void *base, u32 codec_mask)
Zheng Baod0985752011-01-20 04:45:48 +0000155{
156 int i;
157 for (i = 3; i >= 0; i--) {
158 if (codec_mask & (1 << i))
159 codec_init(base, i);
160 }
161}
162
163static void hda_init(struct device *dev)
164{
165 u32 dword;
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800166 void *base;
Zheng Baod0985752011-01-20 04:45:48 +0000167 struct resource *res;
168 u32 codec_mask;
169
170 /* Program the 2C to 0x437b1002 */
171 dword = 0x43831002;
172 pci_write_config32(dev, 0x2c, dword);
173
174 /* Read in BAR */
175 /* Is this right? HDA allows for a 64-bit BAR
176 * but this is only setup for a 32-bit one
177 */
178 res = find_resource(dev, 0x10);
179 if (!res)
180 return;
181
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800182 base = res2mmio(res, 0, 0);
183 printk(BIOS_DEBUG, "base = 0x%p\n", base);
Zheng Baod0985752011-01-20 04:45:48 +0000184 codec_mask = codec_detect(base);
185
186 if (codec_mask) {
187 printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
188 codecs_init(base, codec_mask);
189 }
190}
191
192static struct pci_operations lops_pci = {
193 .set_subsystem = pci_dev_set_subsystem,
194};
195
196static struct device_operations hda_audio_ops = {
197 .read_resources = pci_dev_read_resources,
198 .set_resources = pci_dev_set_resources,
199 .enable_resources = pci_dev_enable_resources,
200 .init = hda_init,
201 .scan_bus = 0,
202 .ops_pci = &lops_pci,
203};
204
205static const struct pci_driver hdaaudio_driver __pci_driver = {
206 .ops = &hda_audio_ops,
207 .vendor = PCI_VENDOR_ID_ATI,
208 .device = PCI_DEVICE_ID_ATI_SB800_HDA,
209};